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Altera_Forum's avatar
Altera_Forum
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20 years ago

NIOS2 with 8Bit devices on tristate bridge

Outside the fpga is a multiplexed 8 bit device bus with shared 8-bit data 20-bit adr nRD nWR and a couple of not shared nCS and a nINT to each device like LAN chip, Profibuschip, NVRAM, R...
Altera_Forum's avatar
Altera_Forum
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20 years ago

If I remember right I was able to eliminate this behavior on specific components (with a dedicated bus) by changing from 'dynamic' to 'native' alignment. I don't think this is going to be the answer for your multiplexed bus. The behavior is undesirable. So is this a bug in the Avalon implementation, a limitation of the design? I'd like to know too.