NIOS2 with 8Bit devices on tristate bridge

Thanks for your comments.

I thought that i am aware of native vs dynamic address alignment. :-(

Some of the external devices are memory and others not.

We need to have

external adr 0 = nios adr 0

external adr 1 = nios adr 1

external adr 2 = nios adr 2

external adr 3 = nios adr 3

all byte size.

This is dynamic mode. but dynamic as mentioned on top of page 90 of the avalon specification says that a 32-bit master port read is two 16bit read on the slave port :-)))) that is what we would call a must not happen .... if software means 16bit then perform 16bit or twice an 8bit access

native mode would produce some gaps as only the lowest 8 bit are valid

nios adr 0 = ------AA = slave adr 0 = AA

nios adr 4 = ------BB = slave adr 1 = BB

so native mode is node the choice for us, a this would make it impossible for the software to use structs and other stuff that need the external memory being maped into the nios memory without any gaps or overlaping :-(

so what i think right now is that the only solution could be :

use nativ mode

use the byteenable signals to determine what byte(s) are selected

make datawidth 32bits to avalon

and loop the external access until all selected bytes are accessed.

what means that if software performs an 8 bit transfer the loop will do only 1 access and for 16bit 2 accesses.

use waitrequest.

this is a bit anoying.

we have also some 512x8bit internal memory that is written by nios and read out by a verilog module. the other 512x8 memory is written by the verilog and read out by nios.

so the verilog part needs the 8 bit access.

nios must be able to access 8/16/32 bit whatever the software wants.

it would be nice if a read performs like the write. if we write 8bit then there is only one 8bit write access. why can't nios/avalon do this with a read signal and set the "not" selected bits to 0 ?

Has anybody a clue for this, i feel a bit lost about that.

regards.

Michael Schmitt