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anonimcs's avatar
anonimcs
Icon for Contributor rankContributor
2 years ago

Nios2 Helloworld project Memory Overflow

Hi guys,

I'm pretty new to Intel's environment for FPGA development and I need to use the Nios2 core for one of my designs. The design is implemented on MAX10 and I'm using Quartus 21.1 Standard edition on Ubuntu 20.04.

To keep things simple, I have created a Nios 2 application & BSP from template, and used Hello World template for that. In Eclipse, I have pointed to the .sopcinfo file of my Quartus project after I generated HDL and then compiled the design in Quartus for using the template helloworld project for my Nios application. After programming the FPGA; I have first generated the BSP, then Build the BSP and then trying to get a successful build from the helloworld application in order to run it.

The problem I'm having here is an overflow on 2 different addresses of the .elf's sections. I'm using an on-chip RAM of 32K and already included that in my Platform Designer with the correct offset (Base = 0x0000_0000, End = 0x0000_7FFF). As this is the template project and I have changed absolutely nothing, I would expect this to work just out of the box, so not sure what I'm doing wrong / missing. The error messages are given below. 

/home/anonimcs/intelFPGA_s21/21.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.3.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/bin/ld: test_flash_10M25.elf section `.text' will not fit in region `onchip_RAM32k'
/home/anonimcs/intelFPGA_s21/21.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.3.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/bin/ld: address 0xa2c4 of test_flash_10M25.elf section `.rwdata' is not within region `onchip_RAM32k'
/home/anonimcs/intelFPGA_s21/21.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.3.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/bin/ld: address 0xbfe4 of test_flash_10M25.elf section `.bss' is not within region `onchip_RAM32k'
/home/anonimcs/intelFPGA_s21/21.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.3.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/bin/ld: address 0xa2c4 of test_flash_10M25.elf section `.rwdata' is not within region `onchip_RAM32k'
/home/anonimcs/intelFPGA_s21/21.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.3.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/bin/ld: address 0xbfe4 of test_flash_10M25.elf section `.bss' is not within region `onchip_RAM32k'
/home/anonimcs/intelFPGA_s21/21.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/10.3.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/bin/ld: region `onchip_RAM32k' overflowed by 16356 bytes

Just out of curiosity, I had a look at the file 'settings.bsp' and I have seen that the memory's sections (such as heap & stack) have set within LinkerSection blocks that's outside the Setting for the memory itself. I was wondering if this is the usual case. However, just as I mentioned above, I should not have to edit any BSP files when running a template project.

Any help would be appreciated.

Cheers!

Embedded Applications Layer
Nios Cpu

12 Replies

  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    Yea, you should not edit the addresses in the BSP linker script.


    You may try to increase your OCRAM IP size , in the Platform Designer and re-generate your HDL. And check again with the new .sopcinfo.


    You should see in the BSP linker script that your OCRAM size have increase and generate your BSP and build your project again.


    • anonimcs's avatar
      anonimcs
      Icon for Contributor rankContributor
      2 years ago

      Yes, when I enabled the small C library in the BSP editor, then I got rid off these errors.

      But now I have a different issue, that I have missing Software Packages in the BSP editor. Is there a way to install them without uninstalling Eclipse ? I'm specificly interested in "altera_safeclib" package as I want to use the "Generic Quad SPI controller II Intel FPGA IP" to communicate with the external flash we use "MT25QL512ABA". Since that package is missing and I cannot enable it in my BSP settings, when I run "alt_flash_open_dev(NAME_OF_FLASH_IN_SYSTEMH_FILE)" it always returns zero, meaning that it fails to open the device in order to read/write. I have followed the instructions for having Nios2 support in Eclipse (https://www.intel.com/content/www/us/en/support/programmable/articles/000086893.html?wapkw=installation+guides&erpm_id=13401520_ts1708675042469) but this guide is wrong, in step 2 when I extract the tar.gz file, it creates a folder with a name "<downloaded_file_name>" which includes an "eclipse" folder in it. So I supposed I needed to take that "eclipse" folder to one level above and then rename it. Even after that, the extraction in step 4 also ends up pretty much the same, with an additional parent folder above "eclipse_nios2" and therefore it cannot overwrite the renamed folder. I rtied copying it manually into the renamed folder, but then the whole Eclipse crashed and I couldn't run it again anymore. I had to uninstall and re-install the whole Quartus Prime software...

      After reinstalling, the steps in the link didn't end in a different result, I still don't have the software packages I want for the BSP settings. I'd appreciate if you (or another colleague of yours) can assist me with that @EBERLAZARE_I_Intel .

      Note: During the Quartus 21.1 Std's installation, Eclipse Development Software (EDS) for Nios2 was already installed, by using the files/packages Intel provided. I couldn't find any plugin SW packages on the internet either...

      • anonimcs's avatar
        anonimcs
        Icon for Contributor rankContributor
        2 years ago

        PS: I have tried replacing the Quad SPI IP with "Generic Serial Flash Interface Intel FPGA IP" with checking the option "Enable SPI pins interface" on the Platform Designer, but also that didn't have the BSP package "altera_safeclib". So the proposed solution on the other posts regarding this topic by the employees did not work. Is there another way to get that BSP package somehow ? @EBERLAZARE_I_Intel

  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    Let me check on my side on the altera_safeclib. In the mean time could you send the latest Quartus project file along with the software and BSP? You can archive them all together.


    • anonimcs's avatar
      anonimcs
      Icon for Contributor rankContributor
      2 years ago

      Hi, which Quartus project files do you want ? It would be more clear if you specify the file extensions of the files.

  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hi,


    By default, the BSP driver should be enable and disable in the BSP settings such as the "altera_safeclib", which depends on the IP in your .qsys design. I am double checking your design. I shall get back to you.


  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hi,


    My apologies, I am a bit caught up on my side, I shall get the replies and update for your later today.


    Thanks again for your patience.


  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hi,


    We regret to inform you that, unfortunately the HAL API is only available in the Quartus Pro version:

    https://www.intel.com/content/www/us/en/docs/programmable/683419/23-1-20-2-3/hal-driver.html

    Note: The Intel HAL Driver is supported in Intel® Quartus® Prime Pro Edition software only.


    Since this ticket initial issue is solved, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.



    p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.