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Balerion's avatar
Balerion
Icon for Occasional Contributor rankOccasional Contributor
5 months ago
Solved

Nios-V .elf download failure

Hi all,
I am trying to download two simple Nios-V apps using RiscFree IDE to my target boards. One of my board has Cyclone-V and the other has Arria-10. My main.cpp files are same but their BSPs are different since boards are different. My app is so simple such that it has a printf printing hello world from jtag uart. However, I am not able to download it to the target. It gives me error as written below, when I try to download it to the board that has Arria-10

--------------------------------
Initializing connection...
Cannot set the JTAG Frequency, continuing with auto adjust mode.
Error occured during enumeration of RISC-V harts(no hart found).

--------------------------------
When I try to download the other app to Cyclone-V it also gives me error the

---------------------------------
Initializing Connection ...

Unable to setup adaptive clock.

Internal error. Couldn't halt the target timeout occured.

Error occured attempting to halt the target during discovery.

---------------------------------

I don't know what the problem are. Could you please help me about that.

Sincerely,

Balerion

Nios Cpu
  • BoonkhaiN_Altera's avatar
    BoonkhaiN_Altera
    5 months ago

    Hi Balerion,

    When you are able to download the elf using the --go command, it is likely that your setup on the board is correct already

    There is an update by the way. I tried the command

    *****************************************************************
    "niosv-download.exe app.elf --go"

    -> Hello Nios V World!

    *****************************************************************

    And you saw this error when trying to connect with RiscFree

    Initializing connection ...
    Cannot set the JTAG frequency, continuing with auto adjust mode
    Connected to target device with IDCODE 0x2e240dd using USB-Blaster-2 (1) via JTAG at 24.00MHz.
    Info : Active Harts Detected : 1
    Info : Core[0] Hart[0] is in halted state
    Info : [0] System architecture : RV32
    Info : [0] Number of hardware breakpoints available : 1
    Info : [0] Number of program buffers: 8
    Info : [0] Number of data registers: 2
    Info : [0] Memory access -> Program buffer
    Info : [0] Memory access -> Abstract access memory
    Info : [0] CSR & FP Register access -> Abstract commands

    Waiting for debugger connection on port 56767.
    Press 'Q' to Quit.

    This could be your RiscFree's setting or your host system's setting not set correctly.

    Likely Root Causes
    GDB Server launched by risc free failes to connect IDE cannot detect the prompt (gdb) migh due to the following

    a) Firewall/antivrus is blocking the local host port access

    b) IDE times out before connection is established

    c) There is a mismatch in how the debug config launches

    Possible Fix

    a) Temporarily disable antivirus / firewall

    b) Try launch RiscFree as administrator

    c) Increase debugger timeout (if IDE allows)

    Please let me know the result after you try the step and provide screenshot if possible.

    Regards,

    Boon Khai

28 Replies

  • BoonkhaiN_Altera's avatar
    BoonkhaiN_Altera
    Icon for Occasional Contributor rankOccasional Contributor
    5 months ago

    Hi Balerion,

    You have two board, Cyclone-V and Arria-10, and you were saying with the same main.cpp and the same steps, loading into Cyclone-V works but not Arria-10?

    You can try check with

    1) Quartus programmer jtag chain by running

    jtagconfig

    2) check that the nios-v processor is actually present and makesure your sof file includes a nios v processor, if the bitstream doest not instantiate a nios-v core the debugger wont find any risc-v harts (hence "no hart found" error), please make sure the bitstream is programmed first

    3) verify BSP and platform configuration and make sure your BSP is generated from a platform designer system that includes required peripheral eg: JTAG UART, clock and reset, memory map etc.

    Regards,

    Boon Khai

    • Balerion's avatar
      Balerion
      Icon for Occasional Contributor rankOccasional Contributor
      5 months ago

      Hi BoonkhaiN,

      Actually I couldn't download .elf to the both device.

      For Cyclone-V board,

      I used Quartus Prime 24.1 Standard version. My design is synthesized with it. Then I generated my BSP using niosv shell of Quartus 24.1 std. I used the command "niosv-bsp -c -t=hal --sopcinfo=system.sopcinfo bsp/settings.bsp" to generate the BSP then for the app, I used the command "niosv-app -a=app -b=bsp -s=app/hello.cpp". Then I import the Nios-V CmakeList project into RiscFree IDE then compiled it. However, When I try to download it to the target it gave me error as I said in the previous post. Which is,

      *****************************************************************************

      Initializing Connection ...

      Unable to setup adaptive clock.

      Internal error. Couldn't halt the target timeout occured.

      Error occured attempting to halt the target during discovery.

      *****************************************************************************

      I can download .sof through Quartus Programmer. I can see the fpga in Jtag Chain. I can also open juart-teminal from console. I can see the target device and Nios-v core through RiscFree IDE Debug Configuration. However I couldn't download my .elf to the target.

      For Arria-10 Board,

      I used Quartus Prime 24.3 Pro version. My design is synthesized with it. Then I generated my BSP using niosv shell of Quartus 24.3 pro. I was thinking of using .sopcinfo file to generate bsp however, I read that it is discarded from currnet CLI interface commands. So that, I used the command "niosv-bsp -c -p=system.qpf -s=system.qsys -t=hal bsp/settings.bsp" to generate the BSP then for the app, I used the command "niosv-app -b=bsp -a=app -s=app/hello.cpp". Then I import the Nios-V CmakeList project into RiscFree IDE then compiled it. However, When I try to download it to the target it gave me error as I said in the previous post. Which is,

      *****************************************************************************

      Initializing connection...
      Cannot set the JTAG Frequency, continuing with auto adjust mode.
      Error occured during enumeration of RISC-V harts(no hart found).

      *****************************************************************************

      I can download .sof through Quartus Programmer. I can see the fpga in Jtag Chain. I can also open juart-teminal from console. I can see the target device and Nios-v core through RiscFree IDE Debug Configuration. However I couldn't download my .elf to the target.

      I couldn't get the problem in both case, Is there anything you suggest me to do?

      Thanks,

      Balerion

    • Balerion's avatar
      Balerion
      Icon for Occasional Contributor rankOccasional Contributor
      5 months ago

      Hi,


      I run "jtagconfig" in niosv shell and the output is below the output is for Arria-10 device. I didn't do it for Cyclone-V. If you want I can also share that.

      Thanks,
      *************
      > jtagconfig


      1) USB-BlasterII [USB-1]
      02E240DD 10AX048E(1|2|3|3ES|4|4ES)/..
      **************

      Balerion

  • BoonkhaiN_Altera's avatar
    BoonkhaiN_Altera
    Icon for Occasional Contributor rankOccasional Contributor
    5 months ago

    Hi please share the jtagconfig for Cyclone-V as well

    run with the "jtagconfig -d" for both devices.

    • Balerion's avatar
      Balerion
      Icon for Occasional Contributor rankOccasional Contributor
      5 months ago

      Hi
      I run the command "jtagconfig -d" for both devices. Here is the result.

      For Arria-10 board:


      1) USB-BlasterII [USB-1]
      (JTAG Server Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition)
      02E240DD 10AX048E(1|2|3|3ES|4|4ES)/.. (IR=10)
      Design hash 659832DA50C1CCAFD154
      + Node 30006E00 Signal Tap #0
      + Node 30006E01 Signal Tap #1
      + Node 30006E02 Signal Tap #2
      + Node 30006E03 Signal Tap #3
      + Node 30006E04 Signal Tap #4
      + Node 30006E05 Signal Tap #5
      + Node 30006E06 Signal Tap #6
      + Node 30006E07 Signal Tap #7
      + Node 30006E08 Signal Tap #8
      + Node 08986E00 Nios V #0
      + Node 0C006E00 JTAG UART #0
      + Node 0C206E00 JTAG PHY #0
      + Node 0C206E01 JTAG PHY #1

      Captured DR after reset = (02E240DD) [32]
      Captured IR after reset = (155) [10]
      Captured Bypass after reset = (0) [1]
      Captured Bypass chain = (0) [1]
      JTAG clock speed 24 MHz


      *****************************************************************

      For Cyclone-V board:

      1) USB-BlasterII [USB-1]
      (JTAG Server Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition)
      02B130DD 5CE(BA7|FA7|FA7ES) (IR=10)
      Design hash BCF7B2F2148F6CA555BF
      + Node 00486E00 Source/Probe #0
      + Node 08986E00 Nios V #0
      + Node 0C006E00 JTAG UART #0
      + Node 0C206E00 JTAG PHY #0
      + Node 00486E01 Source/Probe #1
      + Node 0C206E01 JTAG PHY #1
      + Node 30006E2A Signal Tap #42
      + Node 30006E3C Signal Tap #60
      + Node 30006E29 Signal Tap #41

      Captured DR after reset = (02B130DD) [32]
      Captured IR after reset = (155) [10]
      Captured Bypass after reset = (0) [1]
      Captured Bypass chain = (0) [1]
      JTAG clock speed 24 MHz

      Thanks,

      Balerion

  • BoonkhaiN_Altera's avatar
    BoonkhaiN_Altera
    Icon for Occasional Contributor rankOccasional Contributor
    5 months ago

    I see, so you are connecting to the board through jtagserver.

    Is your device consist of HPS? or it is just FPGA.

    And also you were saying that you able to

    1) download .sof through Quartus Programmer.
    2) can see the fpga in Jtag Chain.(the jtagconfig command)
    3) can also open juart-teminal from console.
    4) can see the target device and Nios-v core through RiscFree IDE Debug Configuration.

    Wonder if you can share your design? would like to cross check if the debug component is loaded, I will take the file to consult with the subject matter expert in our team.

    • Balerion's avatar
      Balerion
      Icon for Occasional Contributor rankOccasional Contributor
      5 months ago

      Hi,

      Both of my device are just FPGA. I want to ask that where do you expect the problem to occur in this situation? I mean, does it seem to be at software side or fpga side?

      Thanks,

      Balerion

  • BoonkhaiN_Altera's avatar
    BoonkhaiN_Altera
    Icon for Occasional Contributor rankOccasional Contributor
    5 months ago

    Hi Balerion,

    We are not sure yet at the moment, if you don't mind, could you please share the FPGA design? so I can consult the subject matter expert in our team.

  • Jeet14's avatar
    Jeet14
    Icon for Frequent Contributor rankFrequent Contributor
    5 months ago

    Hi Balerion,


    Any update on the Boonkhai previous comment?


    Regards

    Tiwari


  • Balerion's avatar
    Balerion
    Icon for Occasional Contributor rankOccasional Contributor
    5 months ago

    Hi,

    Currently, I am not able to share the FPGA design directly. But, I have an update in Arria-10 board. I used to get the error

    *****************************************************************
    Initializing connection...
    Cannot set the JTAG Frequency, continuing with auto adjust mode.
    Error occured during enumeration of RISC-V harts(no hart found).

    *****************************************************************

    A few changes done in FPGA design. Currently, I am getting the error as

    *****************************************************************

    Error in services launch sequence
    GDB prompt not read

    and when I look at the console I see,

    Initializing connection ...
    Cannot set the JTAG frequency, continuing with auto adjust mode
    Connected to target device with IDCODE 0x2e240dd using USB-Blaster-2 (1) via JTAG at 24.00MHz.
    Info : Active Harts Detected : 1
    Info : Core[0] Hart[0] is in halted state
    Info : [0] System architecture : RV32
    Info : [0] Number of hardware breakpoints available : 1
    Info : [0] Number of program buffers: 8
    Info : [0] Number of data registers: 2
    Info : [0] Memory access -> Program buffer
    Info : [0] Memory access -> Abstract access memory
    Info : [0] CSR & FP Register access -> Abstract commands

    Waiting for debugger connection on port 56767.
    Press 'Q' to Quit.

    *****************************************************************

    Is there anything here that may help us to solve the problem? What I notice is that core gets in halted state. That may cause such an issue?

    Thanks,

    Balerion

  • BoonkhaiN_Altera's avatar
    BoonkhaiN_Altera
    Icon for Occasional Contributor rankOccasional Contributor
    5 months ago

    Hi,

    "Currently, I am not able to share the FPGA design directly"
    > It is very hard to understand what is your underlying issue if we don't access to your desgin.

    "A few changes done in FPGA design. Currently, I am getting the error as "
    > Can you share what are the changes you made?

  • Jeet14's avatar
    Jeet14
    Icon for Frequent Contributor rankFrequent Contributor
    5 months ago

    Hi Balerion,


    Any update on the Boon Khai response?

    Is it possible to share the design, its difficult to tell what is causing this issue.


    Regards

    Tiwari


    • Balerion's avatar
      Balerion
      Icon for Occasional Contributor rankOccasional Contributor
      5 months ago

      Hi,

      I am still not able to share my design because of company policies. I am working on it. There is an update by the way. I tried the command

      *****************************************************************
      "niosv-download.exe app.elf --go"

      -> Hello Nios V World!

      *****************************************************************

      and it flashed to the board and executed my program. I have seen the output from juart-terminal

      However debug configuration and run configuration through RiscFree Ashling IDE still not working I am getting same error. as I write below

      *****************************************************************

      Error in services launch sequence
      GDB prompt not read

      and when I look at the console I see,

      Initializing connection ...
      Cannot set the JTAG frequency, continuing with auto adjust mode
      Connected to target device with IDCODE 0x2e240dd using USB-Blaster-2 (1) via JTAG at 24.00MHz.
      Info : Active Harts Detected : 1
      Info : Core[0] Hart[0] is in halted state
      Info : [0] System architecture : RV32
      Info : [0] Number of hardware breakpoints available : 1
      Info : [0] Number of program buffers: 8
      Info : [0] Number of data registers: 2
      Info : [0] Memory access -> Program buffer
      Info : [0] Memory access -> Abstract access memory
      Info : [0] CSR & FP Register access -> Abstract commands

      Waiting for debugger connection on port 56767.
      Press 'Q' to Quit.

      This is my current situation.

      Thanks,

      Balerion

      • BoonkhaiN_Altera's avatar
        BoonkhaiN_Altera
        Icon for Occasional Contributor rankOccasional Contributor
        5 months ago

        Hi Balerion,

        Before we proceed further, would you mind sharing the changes you’ve made on your side? I’m currently not sure what has been done, and since the design can’t be shared, it would really help if you could at least outline the steps or actions taken to make it work. This will allow us to understand if the fix you applied is actually correct and aligned with the intended behavior.

        From the beginning, the image couldn't be downloaded, so I’m trying to understand what might have resolved the issue.


        First you are getting this this error:

        I have an update in Arria-10 board. I used to get the error

        *****************************************************************
        Initializing connection...
        Cannot set the JTAG Frequency, continuing with auto adjust mode.
        Error occured during enumeration of RISC-V harts(no hart found).

        and then eventually able to download elf:

        There is an update by the way. I tried the command

        *****************************************************************
        "niosv-download.exe app.elf --go"

        -> Hello Nios V World!

        *****************************************************************

        If you're unable to share your design, could you at least let us know what changes or steps you’ve taken so far?

        Regards,

        Boon Khai.

  • BoonkhaiN_Altera's avatar
    BoonkhaiN_Altera
    Icon for Occasional Contributor rankOccasional Contributor
    5 months ago

    Hi Balerion,

    Thanks for confirming the steps, when you enable the checkbox "Enable Reset From Debug Module" you actually allowing the debug module inside the NIos V processor to assert a soft reset signal to the CPU core during the debugging via JTAG.

    This reset is controlled internally by the RISC V Debug specification and triggered automatically by the debugger when you perform the steps like halting the CPU, download elf, restart the CPU (--go) or reset the cpu into the known state.

    I think that's why initially when the checkbox is not enabled, you get error like (no hart found) because the core stuck in reset from an external logic or maybe in an illegal instruction set or spinning in tight loops with no debug halt support.


    In short the setting that you choose is correct in order to perform this debugging steps.

    Regards,

    Boon Khai

    • Balerion's avatar
      Balerion
      Icon for Occasional Contributor rankOccasional Contributor
      5 months ago

      Hi,

      Yes, that checkbox solve the hart issue. But I can download and execute only through CLI. I am still not be able to use RiscFree IDE. I couldn't solve that problem. Do you have any idea about where it is? Is there any information that may help us to solve this problem?

      Thanks,

      Balerion