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Balerion's avatar
Balerion
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

Nios-V .elf download failure

Hi all, I am trying to download two simple Nios-V apps using RiscFree IDE to my target boards. One of my board has Cyclone-V and the other has Arria-10. My main.cpp files are same but their BSPs are...
Nios Cpu
  • BoonkhaiN_Altera's avatar
    BoonkhaiN_Altera
    11 months ago

    Hi Balerion,

    When you are able to download the elf using the --go command, it is likely that your setup on the board is correct already

    There is an update by the way. I tried the command

    *****************************************************************
    "niosv-download.exe app.elf --go"

    -> Hello Nios V World!

    *****************************************************************

    And you saw this error when trying to connect with RiscFree

    Initializing connection ...
    Cannot set the JTAG frequency, continuing with auto adjust mode
    Connected to target device with IDCODE 0x2e240dd using USB-Blaster-2 (1) via JTAG at 24.00MHz.
    Info : Active Harts Detected : 1
    Info : Core[0] Hart[0] is in halted state
    Info : [0] System architecture : RV32
    Info : [0] Number of hardware breakpoints available : 1
    Info : [0] Number of program buffers: 8
    Info : [0] Number of data registers: 2
    Info : [0] Memory access -> Program buffer
    Info : [0] Memory access -> Abstract access memory
    Info : [0] CSR & FP Register access -> Abstract commands

    Waiting for debugger connection on port 56767.
    Press 'Q' to Quit.

    This could be your RiscFree's setting or your host system's setting not set correctly.

    Likely Root Causes
    GDB Server launched by risc free failes to connect IDE cannot detect the prompt (gdb) migh due to the following

    a) Firewall/antivrus is blocking the local host port access

    b) IDE times out before connection is established

    c) There is a mismatch in how the debug config launches

    Possible Fix

    a) Temporarily disable antivirus / firewall

    b) Try launch RiscFree as administrator

    c) Increase debugger timeout (if IDE allows)

    Please let me know the result after you try the step and provide screenshot if possible.

    Regards,

    Boon Khai

BoonkhaiN_Altera's avatar
BoonkhaiN_Altera
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi Balerion,

You have two board, Cyclone-V and Arria-10, and you were saying with the same main.cpp and the same steps, loading into Cyclone-V works but not Arria-10?

You can try check with

1) Quartus programmer jtag chain by running

jtagconfig

2) check that the nios-v processor is actually present and makesure your sof file includes a nios v processor, if the bitstream doest not instantiate a nios-v core the debugger wont find any risc-v harts (hence "no hart found" error), please make sure the bitstream is programmed first

3) verify BSP and platform configuration and make sure your BSP is generated from a platform designer system that includes required peripheral eg: JTAG UART, clock and reset, memory map etc.

Regards,

Boon Khai

  • Balerion's avatar
    Balerion
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Hi BoonkhaiN,

    Actually I couldn't download .elf to the both device.

    For Cyclone-V board,

    I used Quartus Prime 24.1 Standard version. My design is synthesized with it. Then I generated my BSP using niosv shell of Quartus 24.1 std. I used the command "niosv-bsp -c -t=hal --sopcinfo=system.sopcinfo bsp/settings.bsp" to generate the BSP then for the app, I used the command "niosv-app -a=app -b=bsp -s=app/hello.cpp". Then I import the Nios-V CmakeList project into RiscFree IDE then compiled it. However, When I try to download it to the target it gave me error as I said in the previous post. Which is,

    *****************************************************************************

    Initializing Connection ...

    Unable to setup adaptive clock.

    Internal error. Couldn't halt the target timeout occured.

    Error occured attempting to halt the target during discovery.

    *****************************************************************************

    I can download .sof through Quartus Programmer. I can see the fpga in Jtag Chain. I can also open juart-teminal from console. I can see the target device and Nios-v core through RiscFree IDE Debug Configuration. However I couldn't download my .elf to the target.

    For Arria-10 Board,

    I used Quartus Prime 24.3 Pro version. My design is synthesized with it. Then I generated my BSP using niosv shell of Quartus 24.3 pro. I was thinking of using .sopcinfo file to generate bsp however, I read that it is discarded from currnet CLI interface commands. So that, I used the command "niosv-bsp -c -p=system.qpf -s=system.qsys -t=hal bsp/settings.bsp" to generate the BSP then for the app, I used the command "niosv-app -b=bsp -a=app -s=app/hello.cpp". Then I import the Nios-V CmakeList project into RiscFree IDE then compiled it. However, When I try to download it to the target it gave me error as I said in the previous post. Which is,

    *****************************************************************************

    Initializing connection...
    Cannot set the JTAG Frequency, continuing with auto adjust mode.
    Error occured during enumeration of RISC-V harts(no hart found).

    *****************************************************************************

    I can download .sof through Quartus Programmer. I can see the fpga in Jtag Chain. I can also open juart-teminal from console. I can see the target device and Nios-v core through RiscFree IDE Debug Configuration. However I couldn't download my .elf to the target.

    I couldn't get the problem in both case, Is there anything you suggest me to do?

    Thanks,

    Balerion