Forum Discussion
Occasional ContributorNIOS SDK tools don't see memory region
We use an Arrow LPDDR controller from the BeMicro designs back with Quartus 12.
I have a CIV E design in Quartus 21 lite with a NIOS II F.
In platform designer, the NIOS vector selection drop-down boxes have the selection for mddr_ctrl_0.avalon_slave, and appears to generate the system successfully along with the sopcinfo file appears to have all the necessary items.
The tcl file is from a previous version, but it does have "is_memory_device" set to true.
The bsp generation scripts show the following:
Executing: wsl nios2-bsp hal . ../../Aggs.sopcinfo --cpu-name nios2_gen2_0 (D:\Altera\Kits\PCIe-AGGS\software\bsp)
nios2-bsp: Using /mnt/d/intelfpga_lite/21.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl to set system-dependent settings.
nios2-bsp: Creating new BSP because ./settings.bsp doesn't exist.
nios2-bsp: Running "nios2-bsp-create-settings.exe --sopc d:/Altera/Kits/PCIe-AGGS/Aggs.sopcinfo --type hal --settings ./settings.bsp --bsp-dir . --script d:/intelfpga_lite/21.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl --cpu-name nios2_gen2_0"
INFO: Creating BSP settings file...
INFO: nios2-bsp-create-settings --sopc d:/Altera/Kits/PCIe-AGGS/Aggs.sopcinfo --type hal --settings ./settings.bsp --bsp-dir . --script d:/intelfpga_lite/21.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl --cpu-name nios2_gen2_0
INFO: Initializing SOPC project local software IP
INFO: [Info] <b>D:/Altera/Kits/PCIe-AGGS/*</b> matched 112 files in 0.10 seconds
INFO: [Info] <b>D:/Altera/Kits/PCIe-AGGS/*/*_sw.tcl</b> matched 0 files in 0.00 seconds
INFO: [Info] <b>D:/Altera/Kits/PCIe-AGGS/ip/**/*_sw.tcl</b> matched 0 files in 0.00 seconds
INFO: [Info] <b>D:/Altera/Kits/ip/**/*_sw.tcl</b> matched 0 files in 0.00 seconds
INFO: Finished initializing SOPC project local software IP. Total time taken = 2 seconds
INFO: Searching for BSP components with category: driver_element
INFO: Searching for BSP components with category: software_package_element
INFO: Found Flash Memory: epcs_flash_controller_0 for CPU: nios2_gen2_0
INFO: Loading drivers from ensemble report.
INFO: Finished loading drivers from ensemble report.
INFO: Tcl message: "STDIO character device is jtag_uart"
INFO: Tcl message: "System timer device is sys_clk_timer"
SEVERE: CPU "nios2_gen2_0" reset memory "mddr_ctrl_0" has no matching memory region.
WARNING: Tcl script "bsp-set-defaults.tcl " error: CPU "nios2_gen2_0" reset memory "mddr_ctrl_0" has no matching memory region.
SEVERE: [Error] altera_hal_linkerx_generator: Required linker section mappings do not exist: "[.entry, .exceptions, .rodata, .rwdata, .text, .bss, .heap, .stack]"
SEVERE: [Error] altera_hal_linkerx_generator: Required linker section mappings do not exist: "[.entry, .exceptions, .rodata, .rwdata, .text, .bss, .heap, .stack]"
SEVERE: nios2-bsp-create-settings failed.
nios2-bsp: nios2-bsp-create-settings.exe failed
I tried digging into the tcl files that print those messages, but I think the .exe is writing those errors.
Help!!
34 Replies
bob_bitchenEven though the compiler / linker won't acknowledge any memory, the hardware can still test it. Q21.1 lite
EBERLAZARE_I_IntelRegular Contributor
Hi,
Thanks for the feedback and attached design, I will try to test that one out.
- EBERLAZARE_I_Intel
Hi,
I am seeing the same as your working output that you attached, I haven't seen the error in the BSP Editor problems from my side,.
My steps was getting your latest design, upgraded to 21.1 lite, then use the sopcinfo for Nios II EDS hello world example, all build are fine.
Could you retry the above and see if the fresh steps could be working or if it still reports error let me know.
- bob_bitchenTry using the mddr in the linker script. Or set it to the reset vector in the Nios.
- bob_bitchen
The original title was "
- bob_bitchen
Bump
- bob_bitchen
I used Quartus 18.1 with the Cygwin Nios EDK tools, and it has the same bug.
The tools were broken by Intel prior to WSL.
- KennyT_altera
Super Contributor
Hi,
Sorry to inform that it take longer time to do the investigation on this bug. Will get back to you more finding as soon as we can.
Thanks
- EBERLAZARE_I_Intel
Hi,
Upon inspecting the design in Platform Designer, the error is related the reset in the Nios II, commonly resets are UFM, QSPI, EPCQ, OCRAM, CFI:
The mobile_ddr seems to be just a controller. For your device Cyclone IV you can either source the reset to EPCQ or OCRAM based on above link examples, you should adjust accordingly.
- bob_bitchenWe use this ram as the boot vector for debugging purposes. The vector is set to the epcs for actual usage. Either way, this IS a functioning design in earlier versions of quartus. The new bug you introduced is trying to get any of the elf file into the DDR. The BSP editor refuses to use this ram from q18 and up. Whatever processes the sopcinfo file was broken as soon Intel changed it. Please read the whole problem here. Thank you
- EBERLAZARE_I_Intel
Hi,
In that case, for workaround, we could add another EPCQ flash controller in the design as a workaround for the mddr?
With this are you okay, if we proceed to test this?
- bob_bitchenAnything that you can do to get the mddr memory region to show up in the drop-down box in the linker script is a solution
- bob_bitchen
The SDK could care less about the function of each memory device. Confirmed.
All debugging can be done in a single memory device of R/W configuration.
- EBERLAZARE_I_Intel
Hi,
I confirm with our internal team, that the Reset vector doesn't support external RAM, it must be a non-volatile memory. So you need to set it to the EPCQ, you need to follow the steps for EPCQ below to replace the old EPCQ IP with the Intel FPGA Serial Flash Controller II for your new designs:
Also, in the newer Quartus, you do no require the Pipeline bridge, you can direct connect as shown above example.
Your application can be stored in the RAM.
Supported memories as reset vectors:
- bob_bitchen
OK, but this doesn't make the ram available to the SDK. That is the problem I'm trying to solve here.
We used to be able to target the ddr device prior to Quartus 18, but 18 and above there is a bug introduced by Intel that doesn't allow the mddr to be a memory region for the linker.
