Forum Discussion

Occasional Contributor

3 years ago

NIOS SDK tools don't see memory region

We use an Arrow LPDDR controller from the BeMicro designs back with Quartus 12. I have a CIV E design in Quartus 21 lite with a NIOS II F. In platform designer, the NIOS vector selection drop-do...

EBERLAZARE_I_Intel

Regular Contributor

3 years ago

Hi,

Upon inspecting the design in Platform Designer, the error is related the reset in the Nios II, commonly resets are UFM, QSPI, EPCQ, OCRAM, CFI:

https://www.intel.com/content/www/us/en/docs/programmable/683689/current/processor-booting-methods.html

The mobile_ddr seems to be just a controller. For your device Cyclone IV you can either source the reset to EPCQ or OCRAM based on above link examples, you should adjust accordingly.

bob_bitchen

Occasional Contributor

3 years ago

We use this ram as the boot vector for debugging purposes. The vector is set to the epcs for actual usage. Either way, this IS a functioning design in earlier versions of quartus. The new bug you introduced is trying to get any of the elf file into the DDR. The BSP editor refuses to use this ram from q18 and up. Whatever processes the sopcinfo file was broken as soon Intel changed it. Please read the whole problem here. Thank you

Forum Discussion

NIOS SDK tools don't see memory region

Recent Discussions

Correct way to use mSGDMA with a NIOSV/m processor on a MAX10 FPGA

Nios-V on Cyclone IV

Unable to load Ashling Riscfree NiosV libraries

University Program IP for NiosV

Nios II IDE File Name too long error