NIOS II/s - No output in console

Could you make the software flash a LED, or could you run it in the debugger, to see if it is running?

Did the JTAG UART base address change when you modified your system in SOPC builder? If yes are you sure the BSP was regenerated with the updated configuration information?

Just tried the debugger, and it says the following:

.gdbinit: No such file or directory.

Reading symbols from C:/Users/.../Documents/DE1/software/MyProj/MyProj.elf...done.

Current language: auto

The current source language is "auto; currently asm".

Stopped due to shared library event

You can check that the base addresses in the BSP's system.h file match the ones from the SOPC builder project. Do you have the system ID component, and is system ID verification enabled in Eclipse? It should be by default, and it's a good way to check that the BSP matches the configuration currently present in the FPGA.

As for the debugger error I've never seen en error like that, I'm sorry but I have no idea what it means...

Yes, the base addresses are matching. System ID verification is enabled. But no output until now.

I have also tried creating whole project from scratch again, selecting NIOS II/s from the beginning but it gives me an ELF file error and shows the following in the console:

There are no Nios II CPUs with debug modules available which match the values

specified. Please check that your PLD is correctly configured, downloading a

new SOF file if necessary.

If anyone wants to replicate my system to check the error, then these are the details:

Development board - DE1

In SOPC builder:

External Clock 50 MHz

NIOS II/s processor with Hardware multiply and divide

On-chip memory (RAM or ROM) - 16384 bytes

JTAG UART

SDRAM Controller - Presets: Custom, Datawidth 16 bits, Chip select 1, Banks 4, Address width 12x8

System ID Peripheral

SD Card interface

Character LCD

Audio and Video Config, On-board peripherals, DE1 board, auto-initialize, Audio-in path: microphone, Audio-out: Enable DAC, Bit length 16, Sampling rate 32 kHz

PIO (input) - SW[7..0]

PIO (output) - LEDR[7..0]

In Quartus, all pin assignments are according to the DE1 board

LCD connections:

LCD_data[7..0] = GPIO_0[7..0]

LCD_E = GPIO_0[8]

LCD_RW = GPIO_0[9]

LCD_RS = GPIO_0[10]

SDRAM PLL is also generated using MegaWizard Plug-in manager.

All settings for this PLL are taken from the SDRAM tutorial included in the DE1 CD that came with the board. Found that same tutorial here: http://users.ece.gatech.edu/~hamblen/de1/de1_cdrom/de1_tutorials/tut_de2_sdram_verilog.pdf

I hope that is all what is required. There are some minor additions/corrections as well, like assigning the SD Card pins, and selecting 'Use as regular I/O' for nCEO pins from Device and pin options.

Please let me know if any of you succeeds in running this system.

--- Quote Start ---

There are no Nios II CPUs with debug modules available which match the values

specified. Please check that your PLD is correctly configured, downloading a

new SOF file if necessary.

--- Quote End ---

It looks like the FPGA didn't load the configuration properly. As long as you have a .sof file with a Nios CPU, it should be detected in the JTAG chain, even if there is something else wrong in the design (clocks, reset...). Are you sure you uploaded the correct .sof file to the FPGA, and that no error occurred during the upload? Could you have power supply problems on the board, that could cause the FPGA to reset? Could you check the nStatus and Config_Done pins?

Check also that you are using the correct .sof file. If you are using an IP for which you don't have a license (such as Nios II/s, Nios II/f, or some memory controllers) then Quartus will generate a file with a _time_limited.sof suffix.