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There are no Nios II CPUs with debug modules available which match the values
specified. Please check that your PLD is correctly configured, downloading a
new SOF file if necessary.
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It looks like the FPGA didn't load the configuration properly. As long as you have a .sof file with a Nios CPU, it should be detected in the JTAG chain, even if there is something else wrong in the design (clocks, reset...). Are you sure you uploaded the correct .sof file to the FPGA, and that no error occurred during the upload? Could you have power supply problems on the board, that could cause the FPGA to reset? Could you check the nStatus and Config_Done pins?
Check also that you are using the correct .sof file. If you are using an IP for which you don't have a license (such as Nios II/s, Nios II/f, or some memory controllers) then Quartus will generate a file with a _time_limited.sof suffix.
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