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Altera_Forum's avatar
Altera_Forum
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20 years ago

Nios II and separate WRITE_N signal to CFI Flash

Hi,

It has been long time I played with Nios II, my first attempts were abandoned due to the project change. Now I am blessed with another project which would have a Nios II as a CPU candidate and I am playing a little with SOPC/Quartus II 5.1

Here is my problem. I have Nios II with tristate bus bridge (called mem_bus below) and I connect to this bus external SRAM and CFI FLASH chip.

Here is how my top level SOPC looks like:

http://voila.pl/91gg9/?1

Here are settings for SRAM and FLASH memory interfaces:

http://voila.pl/91gg9/?2

http://voila.pl/91gg9/?3

And the partial snapshot of the Quartus symbol:

http://voila.pl/91gg9/?4

My question is: why "write_n_to_the_FLASH" signal is not shared with the rest of the write_n signals. In other words, why do I have separate write_n signal instead using mem_bus_readn/mem_bus_writen signals for both SRAM and FLASH ?

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    I have asked that myself too ...

    i finaly ended up with an and2 that connects to both nwrite signals (one from flash one from the other parts) and connects to the output port that leaves the fpga.

    if you find a solution how to get rid of that additional write enable, please post it here.

    Regards.

    Michael
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    --- Quote Start ---

    originally posted by pszemol@Mar 6 2006, 11:15 PM

    my question is: why "write_n_to_the_flash" signal is not shared with the rest of the write_n signals. in other words, why do i have separate write_n signal instead using mem_bus_readn/mem_bus_writen signals for both sram and flash ?

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=13165)

    --- quote end ---

    --- Quote End ---

    The SOPC builder CFI Flash declares the write signal as not shared signal.

    In fact, if you open the system ptf you should find somethig like:

    MODULE FLASH

    {

    ...

    PORT_WIRING

    {

    ...

    PORT write_n

    {

    width = "1";

    is_shared = "0";

    direction = "input";

    type = "write_n";

    }

    So SOPC Builder generates one write signal for the SRAM (mem_bus_writen - shared bus signal) and one for the FLASH (write_n_to_the_FLASH - not shared).

    As this is not modifiable in the GUI, you could manually edit the ptf, putting

    is_shared = "1";

    to have a single, shared, write signal.

    Hope this helps.
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    I seem to be having a problem with read_n being shared and write_n not. When I create a CFI flash component in my system, it generates the read_n as a shared signal (namely, a signal of the tristate bridge). With this setting, I am unable to use the flash (using the standard example memtest.c program, on the Stratix II s60ES FPGA).

    http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif

    However, in the examples directory, if I look into the .ptf of the full_featured example, there the read_n of the flash is not shared but rather is a separate signal. Using full_featured as the .sof, I&#39;m able to successfully test the flash via memtest.c !

    Has anyone encountered this problem ?

    Is it possible to force SOPC builder to "un-share" the read_n signal of the flash ? I guess I can change the .ptf directly, but my change will be overridden by SOPC builder when I generate the system.
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    --- Quote Start ---

    originally posted by pszemol@Mar 12 2006, 05:35 PM

    thank you luca, this is very good observation! http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/smile.gif

    i wonder now if this is just a bug, or intentional...

    anyway, i have modified ptf file to correct write_n signal

    and we will see how long my change will stay there...

    thanks!

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=13346)

    --- quote end ---

    --- Quote End ---

    No bug:

    if you specify shared you get a signal with the name of the bus,

    if you specify not shared you get individual signal for each peripheral,

    using both you get both

    ptf manual editing is not reccomended if you are not familiar with it, anyway the modification will remain also after SOPC generation and regeneration, unless you delete the component
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    --- Quote Start ---

    originally posted by luca@Mar 13 2006, 12:29 PM

    no bug:

    if you specify shared you get a signal with the name of the bus,

    if you specify not shared you get individual signal for each peripheral,

    using both you get both

    ptf manual editing is not reccomended if you are not familiar with it, anyway the modification will remain also after sopc generation and regeneration, unless you delete the component

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=13391)

    --- quote end ---

    --- Quote End ---

    1. There is no option for CFI interface to share or not to share signals.

    2. CFI interface signals seem to be always half-shared (read_n), half-not shared (write_n).

    3. Problem does not appear when I use CFI flash and IDT71V416 predefined SRAM component interface for EP1C20 eval board.
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    By the way, my problem turned out to be unrelated to the separate write_n signal. It appears that it&#39;s not possible to use the CFI flash drived when "Reduced device drivers" is set in the System Library properties.

  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    Thanks for all of you!

    I just modified the sram`s class.ptf file,

    and fogot to modify the flash`s class.ptf,

    so leaving the"write_to_the_cfi_flash" pin separate.