Nios crashes when reading from the DDR2

The design uses multiple clock domains, so I've implemented a dual-register reset synchronizing circuit for each clock domain's reset in order to have synchronous reset removal. For the DDR2, the "global_reset_n_to_the_ddr2" port should be getting the reset from the same domain as its input global osc_clock, correct?

I'm compiling the design you suggested.

thanks,

Andrew

Hey,

I'm still getting that same bug even with the pipeline bridge in there. So, I guess we know it's not the bridge.

Andrew

I assume your design is for a custom board?

Well the reason the NIOS is hanging is most likely because it's waiting for the DDR2 controller to return data but it's never returning it. I have seen this before but your circumstances are different. The most common reason I saw was when there was insufficient pipeline buffering between the processor and the DDR2 controller.

Here are some things to try:

1 - Try making the read buffer larger inside the clock-crossing bridge.

2 - Check that the init_done signal from the DDR2 controller is getting asserted.

3 - Put signaltap in to look at the avalon interface to the DDR2 controller and see what is going on there when a read occurs.

Jake

Hi Boots79,

unfortunately I'm still more or less new to FPGA but I had a simmilar problem.

I forgot to malloc enough space for my framebuffer and overwrote my program code.

As I'm to tired at the moment I'm not able to go through your code step by step. But anyway, I can't find much malloc / free commands. Try to ensure that by yourself ...

Is your program code also stored in this ram?

Maybe thats the right hint ;)

Leo

In SignalTap I checked the init_done and the Avalon signals connected to the DDR2. It seems I may have been wrong about being able to read from the memory.

The init_done always goes high, but I am getting solid 0's for the Avalon signals "ddr2_sdram_s1_readdata" across every "m1_read" trigger. Also, the "readdatavalid" signal is always low.

I'm not sure why I'm getting some valid pixels out, unless the Nios is buffering them and just sending them to the PIO without waiting for the read from the DDR in certain cases.

The timing analysis shows that I am meeting all the requirements, but I guess it's not fully constrained?

Andrew

This is one of those moments where I say "Oh if only I were there I could find the problem." Does your synthesis or fitter report give any alarming messages regarding logic being synthesized away or removed?

Jake

Haha. Well, thanks for helping me out. I'm learning a lot trying to troubleshoot this.

My palm just hit my head because I realized a few pins were not connected this morning when I was testing it. It's the stupidest thing. I'm nowhere near the board right now, but I'll fix it and test it out later.

I noticed I was getting a warning about the ddr pll clk[2] signal not being used. So, I'll see if that warning goes away when I fix the pin assignments. I'm not sure how they ever got deleted in the first place.

Also, for the DE3 board, there's a voltage regulator circuit for each of the 4 different regions where things are connected. It's the first thing you define when you start the design (which for me was a few months ago). A while ago, I commented it out, but the DDR2 takes 1.8 V instead of the default 3.3 V.

I'll let you know if it works.

Andrew

Hey again,

It turns out my pin assignments were made, I was just looking at an out of date project on another computer.

The DE3 voltage regulator circuit controls the I/O levels of the FPGA, but I had already assigned them properly in the pin planner, so including that circuit made no difference.

Jake, you asked about any weird messages? The following assignments from the assignment editor are being ignored by the fitter:

altmemddr_phy_alt_mem_phy_pll_siii:

*half_rate.pll|altpll:altpll_component|altpll_bes2:auto_generated|phasedone

*half_rate.pll|altpll:altpll_component|altpll_bes2:auto_generated|pll1~LOCKED

*half_rate.pll|altpll:altpll_component|altpll_bes2:auto_generated|pll1~FBOUT

*half_rate.pll|altpll:altpll_component|altpll_bes2:auto_generated|clk[0]

*altmemddr_phy_alt_mem_phy_clk_reset_siii:clk|mem_clk_2x

*altmemddr_phy_alt_mem_phy_clk_reset_siii:clk|write_clk_2x

*altmemddr_phy_alt_mem_phy_clk_reset_siii:clk|resync_clk_2x

*altmemddr_phy_alt_mem_phy_clk_reset_siii:clk|measure_clk_1x

*altmemddr_phy_alt_mem_phy_clk_reset_siii:clk|ac_clk_1x

The warning said that they were "assigned to location or region, but does not exist in design." I assume they were removed by the synthesis engine because they were not needed?

Also, should I be explicitly constraining the output data and address lines to the DDR2, or are those constraints taken care of by the auto-generated DDR2 .sdc file?

Thanks,

Andrew

I just wanted to follow up and say that I have it working now. I am writing and reading full frames from the DDR2!

There were actually quite a few things wrong with my design when I first posted on here, but what was really causing the hanging of the Nios was a wrong assignment on the mem_cke pin. The DE3 board has an optional mem_cke[1] assignment, which I had wrongly set for some reason instead of the correct mem_cke[0].

Thanks, Jake, for your help.

Andrew

I'm glad you got it figured out. Have fun.

Jake