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Altera_Forum's avatar
Altera_Forum
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16 years ago

Nios crashes when reading from the DDR2

Hi, I'm trying to setup the DDR2 as a frame buffer for streaming to a display. Currently, I am able to write and read pixels to and from the off-chip DDR2 and communicate with custom ha...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The design uses multiple clock domains, so I've implemented a dual-register reset synchronizing circuit for each clock domain's reset in order to have synchronous reset removal. For the DDR2, the "global_reset_n_to_the_ddr2" port should be getting the reset from the same domain as its input global osc_clock, correct?

I'm compiling the design you suggested.

thanks,

Andrew