Nios crashes when reading from the DDR2

Hey again,

It turns out my pin assignments were made, I was just looking at an out of date project on another computer.

The DE3 voltage regulator circuit controls the I/O levels of the FPGA, but I had already assigned them properly in the pin planner, so including that circuit made no difference.

Jake, you asked about any weird messages? The following assignments from the assignment editor are being ignored by the fitter:

altmemddr_phy_alt_mem_phy_pll_siii:

*half_rate.pll|altpll:altpll_component|altpll_bes2:auto_generated|phasedone

*half_rate.pll|altpll:altpll_component|altpll_bes2:auto_generated|pll1~LOCKED

*half_rate.pll|altpll:altpll_component|altpll_bes2:auto_generated|pll1~FBOUT

*half_rate.pll|altpll:altpll_component|altpll_bes2:auto_generated|clk[0]

*altmemddr_phy_alt_mem_phy_clk_reset_siii:clk|mem_clk_2x

*altmemddr_phy_alt_mem_phy_clk_reset_siii:clk|write_clk_2x

*altmemddr_phy_alt_mem_phy_clk_reset_siii:clk|resync_clk_2x

*altmemddr_phy_alt_mem_phy_clk_reset_siii:clk|measure_clk_1x

*altmemddr_phy_alt_mem_phy_clk_reset_siii:clk|ac_clk_1x

The warning said that they were "assigned to location or region, but does not exist in design." I assume they were removed by the synthesis engine because they were not needed?

Also, should I be explicitly constraining the output data and address lines to the DDR2, or are those constraints taken care of by the auto-generated DDR2 .sdc file?

Thanks,

Andrew