Nios crashes when reading from the DDR2

Haha. Well, thanks for helping me out. I'm learning a lot trying to troubleshoot this.

My palm just hit my head because I realized a few pins were not connected this morning when I was testing it. It's the stupidest thing. I'm nowhere near the board right now, but I'll fix it and test it out later.

I noticed I was getting a warning about the ddr pll clk[2] signal not being used. So, I'll see if that warning goes away when I fix the pin assignments. I'm not sure how they ever got deleted in the first place.

Also, for the DE3 board, there's a voltage regulator circuit for each of the 4 different regions where things are connected. It's the first thing you define when you start the design (which for me was a few months ago). A while ago, I commented it out, but the DDR2 takes 1.8 V instead of the default 3.3 V.

I'll let you know if it works.

Andrew