Forum Discussion
Altera_Forum
Honored Contributor
16 years agoIn SignalTap I checked the init_done and the Avalon signals connected to the DDR2. It seems I may have been wrong about being able to read from the memory.
The init_done always goes high, but I am getting solid 0's for the Avalon signals "ddr2_sdram_s1_readdata" across every "m1_read" trigger. Also, the "readdatavalid" signal is always low. I'm not sure why I'm getting some valid pixels out, unless the Nios is buffering them and just sending them to the PIO without waiting for the read from the DDR in certain cases. The timing analysis shows that I am meeting all the requirements, but I guess it's not fully constrained? Andrew