Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

Nios board couldn't work with SignaltapII

hi:

The board i use is nios pro stratix 1s40,when i program my sof file down to the FPGA, it just ok.

but then i use signaltapII to debug my froject, the case is that it often reload the sof file from the flash device, as i have set the unused pins as input & tri-state, it just impossible .The more strange is that sometimes i change something , like the input clock or some signal, it just could work.

ask for help, thx!

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Are you saying that you can't sample using SignalTap or that your embedded design stopped working? We will need more info to be able to help you out. (Provide as much detail as possible to get the best possible solution)

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    SigTap II and JTAG_UART of NiosII always use JTAG cable. So is it the problem of multi-using JTAG? Is it right to set "stdout" "stderr".. of Nios II to normal "UART" instead of JTAG_UART?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    thank you for reply.

    The fact is that the project i program didn't have a Nios CPU, i want to use SignaltapII to check my project.

    As i set the unused pins as inputs & tri-state , so the CPLD didn't load the sof file from flash,(because the LED "loading"didn't turn on);but as i add signaltapII to my module ,when i program down to the board,CPLD load the sof file from flash,the LED "loading" blinking and then the LED "user" turn on.so the signaltapII just couldn't work.

    The board i use is nios pro stratix 1s40,i think something in signaltapII was set wrong like pins.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    the timing simulation takes me too much time, is there any method beside using signaltapII can check my project?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    the timing simulation takes me too much time, is there any method beside using signaltapII can check my project?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    There is no problem using multiple JTAG devices (Nios II debug module, JTAG Uart, Signaltap II). Also there is no problem using an RS232 (Normal) Uart for terminal I/O.

    <div class='quotetop'>QUOTE </div>

    --- Quote Start ---

    The board i use is nios pro stratix 1s40,i think something in signaltapII was set wrong like pins.[/b]

    --- Quote End ---

    Signal Tap II is non-intrusive so it doesn&#39;t require pins in most cases (you connect it to the internal logic).

    I would check to make sure your sampling rate is defined correctly (remember that the signaltap II clock has to be at least twice as fast as the maximum data clocking rate you are sampling otherwise you will not collect data correctly (golden law of sampling)). Also make sure your trigger conditions are set up correctly.

    Are you saying you see the heartbeat LED blinking with signaltap II present and it just doesn&#39;t sample data or adding it in breaks the entire design (i.e. no LED blinking)?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Hi BadOmen,

    This thread caught my eye, because I was trying to use the IDE debugger and Signal Tap at the sametime, and had no luck with this. The JTAG would just freeze up on me. I can&#39;t remember the errors or warnings that went along with this.

    If this is true using multiple JTAG devices, that is great. Are there any special setups for this?

    Thanks,

    -Baycool
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Hmmmmm maybe you ran into a bug. I had a design that had all three JTAG devices present but perhaps the communication never overlapped. If anyone can recreate this please email me the design so that I can take a look (if it doesn&#39;t target a Nios development board please rip out all the components/logic that are not needed to create this so that I can easily port it to a dev board).

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    If you have a Quartus subscription, you should also have a license for modelsim. Give it a try - it looks scary at the first moment, but it works great if you got into it....

    Another altanative is to connect an external logic analyzer if you can route the interresting signals to some spare pins (only suitable if there are just a few singals of interrest)...
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    thanks BadOmen&#39;s answer, and i think i had found the key to settle the problem.

    Some background: The Nios dev boards have a feature for implementing

    and demonstrating remote reconfiguration of the Stratix/Cyclone

    device. This is implemented by a single IO which is connected to the

    board&#39;s MAX7128 configuration controller - if the FPGA asserts this

    IO, the MAX device will follow the power-on configuration sequence in

    an attempt to boot the FPGA with (presumably) a new FPGA configuration

    stored in flash. However, if this pin is not used in your design, and

    is not reserved as tri-stated, the pin could (and does) float to tell

    the MAX device to perform re-configuration. ¡ª¡ª by Jesse.

    so in normal times, if your project didn&#39;t have nios, u have to set all the unused pins as input & tri-state.

    but when i use signaltapII ,this setting didn&#39;t work.

    so i connect the pld_RECONFIGREQ_n pin to a vcc, that the FPGA wouldn&#39;t sent a reconfig require to CPLD.

    luckly the signaltapII can work now!!!