Altera_Forum
Honored Contributor
14 years agoNeed help::: Error: Node instance "XXX" instantiates undefined entity "XXX"
Hi all,
I am using nios processor to controll the userlogic(verilog) for my project.I have little experience with schematic entry. so I have created the symbol from the verilog code and I have connected both systems. When I try to compile my design I am getting this kind of errors. Error: Node instance "onchip_mem" instantiates undefined entity "processor18_onchip_mem" Error: Node instance "cpu18" instantiates undefined entity "processor18_cpu18" Error: Node instance "jtag_uart18" instantiates undefined entity "processor18_jtag_uart18" Those are just examples I am getting 64 errors(for each part I have used in processor ).Is there anyone having idea about this error. My final design should work exactly like as you see in the picture.