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Altera_Forum
Honored Contributor
14 years agoNeed help::: Error: Node instance "XXX" instantiates undefined entity "XXX"
Hi all, I am using nios processor to controll the userlogic(verilog) for my project.I have little experience with schematic entry. so I have created the symbol from the verilog code and I have c...
Altera_Forum
Honored Contributor
14 years agoSorry for the previous post,
I forgot to add .qip file to my project.But still I have a problem.If you see the schematic you will find a bidirectional bus (data_pio_external to port_0_io ).Is it proper way of connecting bidirectional nodes.Because I am getting some Error: Port "port_0_io[0]" does not exist in macrofunction "inst".