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Altera_Forum
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14 years ago

Need help::: Error: Node instance "XXX" instantiates undefined entity "XXX"

Hi all, I am using nios processor to controll the userlogic(verilog) for my project.I have little experience with schematic entry. so I have created the symbol from the verilog code and I have c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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Sorry for the previous post,

I forgot to add .qip file to my project.But still I have a problem.If you see the schematic you will find a bidirectional bus (data_pio_external to port_0_io ).Is it proper way of connecting bidirectional nodes.Because I am getting some Error: Port "port_0_io[0]" does not exist in macrofunction "inst".

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" i am facing same problem for compilation, but i can't understang what the .qip file is and how to add it to project. please help."