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Altera_Forum
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14 years ago

Need help::: Error: Node instance "XXX" instantiates undefined entity "XXX"

Hi all, I am using nios processor to controll the userlogic(verilog) for my project.I have little experience with schematic entry. so I have created the symbol from the verilog code and I have c...
Altera_Forum's avatar
Altera_Forum
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14 years ago

You should only use bidirectional signals when connecting to i/o ports of the FPGA. Signals inside the FPGA can only go in one direction. I don't think Quartus can synthesize an internal bidirectional bus, it will probably stop with a multiple drivers error.