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Altera_Forum
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14 years ago

Memory verification issue

Hi all,

I have ran into a problem when running Simple Socket Server.

When i am trying to run the program (from on-chip ram memory ) i get the verify failed message :

"

Verifying 00600020 ( 0%)

Verify failed between address 0x600020 and 0x60FFFF

Leaving target processor paused" on nios II console.

I am using Arria II gx (ep2agx260ff36i5n) device and a custom board.The address range in which verification has failed is on chip ram address area.I have tried to run the program from external SSRAM and got the same error,and i have switched to on-chip ram memory in order to isolate the problem. It is important to notice that i am able to run simple programs (such as memory test ,hello world ,blinking leds) either on external SSRAM or on-chip memory without any problems.Any help would be appresciated

Thank You,

Michael.

12 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I assumed that you used the exact same FPGA configuration for the first simple programs... Does it meet all timing requirements?

    Did you use different addresses sections for exceptions/heap/stack between the simple socket server and the other applications you tried? are you sure you have enough on-chip memory to fit the entire SSS application, including stack and heap?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    -"I assumed that you used the exact same FPGA configuration for the first simple programs... Does it meet all timing requirements?"

    How can i know that ?

    -"Did you use different addresses sections for exceptions/heap/stack between the simple socket server and the other applications you tried? "

    Nope.I guess they should all point to the same location of exception vector (whether it is ssram or on-chip ram).Is this correct?

    -"are you sure you have enough on-chip memory to fit the entire SSS application, including stack and heap?"

    Positive.I am able to allocate 500K of internal RAM without a problem.From the console i see "downloaded 305k...." so i guess that the program takes 305k of memory space

    (correct me if i am wrong).Also ,if i am not mistaken,in case of not enough memory space,there are error messages in console indicating that there is not enough space.

    Another thing,i have tried to run lwip-based program,which was run and tested correctly previously on embedded systems development kit.That program occupes less memory space.While trying to run it,i got the same error.I guess it is program size issue,but of course it is unacceptable not to be able running a program above certain size if you have enough memory.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    For the timing requirements, check that all your inputs/outputs and clocks are properly defined and that you don't have any critical warning from timequest. Having a look at the timequest user guide (http://www.alterawiki.com/wiki/timequest_user_guide) may be of some help here.

    I think you are right about the software size, and the remaining of the memory will be used for heap and stack. The application could crash if there isn't enough free memory available, but I don't think it would cause a verification fail.

    I think I would look for a bad timing problem first.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Maybe this is not your case, but I had a similar problem which was related to the addresses of Nios reset and/or exception vectors. Verify them in sopc builder Nios properties.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    what do you mean?those addresses are allocated automatically,to my knowledge,and the offsets are aligned automatically as well.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Sorry. I wrote 'addresses' because this is what sopc builder eventually generates for system.h file,

    but I meant the memory where you want to place the vectors: this is what you actually select in Nios properties.

    So, keep the predefined offsets and try to change the memory selection.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    It is all rather a PITA that the actual failing address (and value) isn't reported ...

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Well, i got a non-comforting solution.This error has nothing to do with program size.I can't run "hello world" example either.I have just removed some added mega-wizard component (altclk) and the error was removed .The thing is that i bump into this error numerous times:

    -When i try to get nios to work above certain frequency (125 Mhz)

    -when i connect sg-dma controller descriptors to descriptor memory instead of ssram bridge (as in standard ethernet example)

    -when i connect 125 Mhz (different) clock output to txclk of TSE mac and altclk component to output (in order to get connection of GMII )

    Anyone has run into similar issue(s) or was it just me ? :)
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    It defenitely looks like a timing problem. Check your sdc constraints and the timequest report.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I have checked,i get some critical warnings from sdc files.But if i fully compile reference example designs,without touching anything (as is) i get the same errors.What can i do to fit the constraints (any ideas would be welcome :) )

    One of possible solutions is that i should look for example designs that are as close to my fpga (and custom board) as possible.One of the options is to use arria II development kit (6g edition) examples.The problem is that the designs aren't just sopc - they do have a bit logic around them.That makes those designs very un-modular (unless someone has a good solution of changing the entity(module) in provided code (verilog/vhdl). (I have failed to build a working design using sopc as symbol block in my top bdf file - even simple hello world example has memory verification issues-probable cause of the problem is that i don't have the same input oscillator clock (20 Mhz of 100 Mhz).Any change could possibly not fit into the constraints)