Memory verification issue

I have checked,i get some critical warnings from sdc files.But if i fully compile reference example designs,without touching anything (as is) i get the same errors.What can i do to fit the constraints (any ideas would be welcome :) )

One of possible solutions is that i should look for example designs that are as close to my fpga (and custom board) as possible.One of the options is to use arria II development kit (6g edition) examples.The problem is that the designs aren't just sopc - they do have a bit logic around them.That makes those designs very un-modular (unless someone has a good solution of changing the entity(module) in provided code (verilog/vhdl). (I have failed to build a working design using sopc as symbol block in my top bdf file - even simple hello world example has memory verification issues-probable cause of the problem is that i don't have the same input oscillator clock (20 Mhz of 100 Mhz).Any change could possibly not fit into the constraints)