JPEG core with NiosII

So where are you Jeroen? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif

Nothing to Say!!! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

Try making your component dynamic instead of native. Dynamic components (typically memory) use byte enables so you shouldn&#39;t run into any width restrictions there.

Better yet, you are probably working a buffer of data so if that&#39;s the case here&#39;s how I&#39;d approach this:

1) Stuff the data into wide on-chip memory buffers

2) Feed your accelerators with data using DMA engines from the on-chip memory buffers

Step two can be done two different ways, you can use a separate DMA engine (available in SOPC Builder) or just build one on the front end of your hardware accelerator. To learn more read the component editor and Avalon memory mapped specification.

Hi guys.

I&#39;m a beginner with Nios II and Quartus II. My developing board mounts a Cyclone II FPGA EP2C35.

I must interface an external Camera (C3088 made of Omnivision OV6620 sensor) with that board but, i don&#39;t know how to do that. I mean, the connection to PROTO1/PROT2, it&#39;s ok, but how create the interface with the internal system?Should i use Avalon MM? I have look to Portable Reference Board project but is really hard to understand.

I hope someone coul help me and give some clear advices

Many thanks

Paolo

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originally posted by tonnoplast@Jan 10 2007, 03:42 AM

hi guys.

i&#39;m a beginner with nios ii and quartus ii. my developing board mounts a cyclone ii fpga ep2c35.

i must interface an external camera (c3088 made of omnivision ov6620 sensor) with that board but, i don&#39;t know how to do that. i mean, the connection to proto1/prot2, it&#39;s ok, but how create the interface with the internal system?should i use avalon mm? i have look to portable reference board project but is really hard to understand.

i hope someone coul help me and give some clear advices

many thanks

paolo

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Avalon-MM should be fine for what you are doing. I would read these documents to learn more:

http://www.altera.com/literature/manual/mnl_avalon_spec.pdf (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf)

http://www.altera.com/literature/hb/qts/qts_qii54005.pdf (http://www.altera.com/literature/hb/qts/qts_qii54005.pdf)

http://www.altera.com/literature/hb/qts/qts_qii54007.pdf (http://www.altera.com/literature/hb/qts/qts_qii54007.pdf)

(I took those links from this page: http://www.altera.com/literature/quartus2/lit-qts-sopc.jsp) (http://www.altera.com/literature/quartus2/lit-qts-sopc.jsp))

Avalon-MM gives you standard interface to conform to so as long as you can make your camera logic in the FPGA meet the specification, then you just feed your HDL through component editor and drop the result into your system. The most basic and common interfaces will have these signals:

writedata (data out to your component)

write (write enable)

chipselect

readdata (data in from your component)

read (read enable, sometimes your logic won&#39;t need it)

address (if you have multiple locations to access in your component)

clk

reset

Thank you badomen. I will have a look again to that documentations.

Another question. Do you think that is possible to catch datas from camera using PIO PORT with IRQ? I mean, read that port everytime a signal(PXCLK) shows a ready pixel byte, and then put that pixel on array.

Thank you

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originally posted by tonnoplast@Jan 12 2007, 03:37 AM

thank you badomen. i will have a look again to that documentations.

another question. do you think that is possible to catch datas from camera using pio port with irq? i mean, read that port everytime a signal(pxclk) shows a ready pixel byte, and then put that pixel on array.

thank you

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The interface doesn&#39;t look like it would support a PIO interface very well. I did a quick search and it looks like you are fed YUV using a clock source from the camera which comes back as back to back data.

I recommend creating a component that takes the data from the camera, stuffs the data into a memory based FIFO, then having an interrupt fire when the FIFO reaches a certain length like half full for example. Then you can have a DMA pull the data out of your component. There could be better methods depending on your system architecture so I would explorer all possibilities before diving into the design.

System Interconnect Fabric Custom Logic

DMA <--- Your custom component (FIFO) <---- Camera

Thank you again. Just because today is Friday i hope you could answer my next question before week end.

As me,you probably had a look to Portable Reference Platform Project in a NiosII forum section.

There,it is used a Camera block and a DMA for Camera.Well, both are descripted in vhdl language,but DMA vhdl&#39;s it&#39;s understandable for me.If you could,say me what do you think of that

Anyway this is my question.I&#39;d like to know if you are agree with me:

1) I must describe my camera in vhdl(structural and functional) for having it available on SOPC builder.Then in Quartus i will do the connection in order to where is placed my camera;

2)Could i use the DMA already present in SOPC for camera data flows?If not,dma vhdl description it&#39;s the only way?

Thank you

Paolo

Sorry...in the post before..the VHDL of DMA it&#39;s NOT understandable for me.

And last thing..i&#39;ve tried to use PIO as i said you. I can&#39;t catch the Pixel clock signal that it&#39;s the fastest and i can&#39;t catch data.So probably PIOs are ko.

Bye

Paolo

Yes, you can create your interface component in VHDL and use it in your SOPC Builder system. The main purpose of that component is to bridge your camera interface signals to the system interconnect fabric. You would still have to connect the camera signals in Quartus via pin assignments.

You shouldn&#39;t have to understand the VHDL that the DMA is written in since the component is completed for you.

PIOs are simply memory mapped registers so that&#39;s why you couldn&#39;t use them for your interface. I recommend that you stuff the data from your camera interface into a small FIFO then map the read side of the FIFO to the system interconnect fabric. If you search the forum I think you&#39;ll find something similar to this in the IP section.

Ok BadOmen.I&#39;ll follow your suggest.

You are really kind...and your Charlie Brown picture really relax "People NiosII shocked" like me http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

See ya!

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/laugh.gif