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Altera_Forum
Honored Contributor
19 years agoJPEG core with NiosII
Hi Every body i am working on project : JPEG core on FPGA Probably i will use NiosII development kit with STRATIX board and i will iterface the JPEG core with the NiosII as a new component so i...
Altera_Forum
Honored Contributor
19 years agoTry making your component dynamic instead of native. Dynamic components (typically memory) use byte enables so you shouldn't run into any width restrictions there.
Better yet, you are probably working a buffer of data so if that's the case here's how I'd approach this: 1) Stuff the data into wide on-chip memory buffers 2) Feed your accelerators with data using DMA engines from the on-chip memory buffers Step two can be done two different ways, you can use a separate DMA engine (available in SOPC Builder) or just build one on the front end of your hardware accelerator. To learn more read the component editor and Avalon memory mapped specification.