JPEG core with NiosII

Here is a good place to start reading: http://www.altera.com/literature/quartus2/lit-qts-sopc.jsp (http://www.altera.com/literature/quartus2/lit-qts-sopc.jsp)

You will want to pay attention to the documents about component editor, developing components, and the Avalon memory mapped interface specification.

What you are attempting is feasible. I don't know anything about your JPEG core but if it is high performance be sure to stuff data into it using a direct memory access (DMA) engine.

I hope that helps get you started

Thanks for the information,

but the main purpose of this project is to ameliorate the previous works concerning JPEG decoder and all related projects, so in reality i want to speed up and accelerate the algorithm by implementing hardware blocks such as DCT, IDCT, Huffmann, Quantifier...

interfaced with Nios.

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originally posted by melomane@Dec 22 2006, 08:17 AM

thanks for the information,

but the main purpose of this project is to ameliorate the previous works concerning jpeg decoder and all related projects, so in reality i want to speed up and accelerate the algorithm by implementing hardware blocks such as dct, idct, huffmann, quantifier...

interfaced with nios.

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=20187)

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Maybe you should check thejpeg compressor core (http://www.opencores.org/projects.cgi/web/jpeg/overview) from opencores.

Avishay

Thanks for the information it&#39;s very important for me

but sorry i still have a question : How can i display the image in format JPEG after compressing it with my own JPEG compressor?

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originally posted by melomane@Dec 26 2006, 08:37 AM

thanks for the information it&#39;s very important for me

but sorry i still have a question : how can i display the image in format jpeg after compressing it with my own jpeg compressor?

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=20216)

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Somehow transfer it to a PC. A flash card, a serial link.

I&#39;m currently working on a JPEG decoder, based on the reference implementation of the Indepedant JPEG Group. I&#39;m developing a few specific hardware accelerators; I have found that memory bandwidth is a major bottleneck (I also have a LCD controller that takes up quite some bandwidth http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif )

For example, my hardware Avalon MM IDCT core takes only 20 or so clock cycles to compute a full 8x8 IDCT including dequantization/descaling/rounding/clamping, but just transferring the coefficients and the resulting pixels components takes many more cycles (195 cycles just to load 64 coefficients in 32 writes (no looping), with a tightly coupled instruction and data memory). In the software version, these transfers took only a small percentage of the total computation time, but now it has become a major bottleneck. (I already have devised another way to speed this up).

Now I have sped up the IDCT, upsampling has become the major bottleneck, taking up over 60% of the total time, as this is basically just data copying.

My goal is to decode a 640x480 4:2:0 file in 100ms, though I think this isn&#39;t a realistic goal unless I use a full hardware JPG decoder http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/tongue.gif (it&#39;s around 550ms now)

I wonder if it&#39;s useful to use SDRAM, as currently I use the Async SRAM on a Nios development kit/Cyclone edition.

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originally posted by jeroen+dec 27 2006, 11:45 pm--><div class='quotetop'>quote (jeroen @ dec 27 2006, 11:45 pm)</div>

--- quote start ---

<!--quotebegin-melomane@Dec 26 2006, 08:37 AM

thanks for the information it&#39;s very important for me

but sorry i still have a question : how can i display the image in format jpeg after compressing it with my own jpeg compressor?

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=20216)

--- quote end ---

--- Quote End ---

Somehow transfer it to a PC. A flash card, a serial link.

I&#39;m currently working on a JPEG decoder, based on the reference implementation of the Indepedant JPEG Group. I&#39;m developing a few specific hardware accelerators; I have found that memory bandwidth is a major bottleneck (I also have a LCD controller that takes up quite some bandwidth http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif )

For example, my hardware Avalon MM IDCT core takes only 20 or so clock cycles to compute a full 8x8 IDCT including dequantization/descaling/rounding/clamping, but just transferring the coefficients and the resulting pixels components takes many more cycles (195 cycles just to load 64 coefficients in 32 writes (no looping), with a tightly coupled instruction and data memory). In the software version, these transfers took only a small percentage of the total computation time, but now it has become a major bottleneck. (I already have devised another way to speed this up).

Now I have sped up the IDCT, upsampling has become the major bottleneck, taking up over 60% of the total time, as this is basically just data copying.

My goal is to decode a 640x480 4:2:0 file in 100ms, though I think this isn&#39;t a realistic goal unless I use a full hardware JPG decoder http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/tongue.gif (it&#39;s around 550ms now)

I wonder if it&#39;s useful to use SDRAM, as currently I use the Async SRAM on a Nios development kit/Cyclone edition.

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=20245)</div>

[/b]

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Thank you Jeroen for your useful information and I think you have done a very good work even the speed up of the software version did not satisfied you. In previous work i have speed up an algorithm which treats the 3D images with a lot of multiplier

adder, and divide. These macroblocs, i have integrated it with two modes : first as custom instructions, and then as new component interfaced with NiosII processor

As a result i have speed up the software version taking over 70%(Version full custom instructions). For the "Component version" i met some difficulties in interfacing my Hardware accelerators with Avalon Bus so I abort this solution http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif . Please if you have some samples of Interfaces to Avalon (VHDL language in preference) in order to add my accelerators as new component. Send it to me and I will be very grateful to you http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

The device targeted is the stratixII (Simulated on Stratix professional Borad) and i have not tried to display some images before.

--- Quote Start ---

originally posted by melomane@Dec 28 2006, 09:57 AM

for the "component version" i met some difficulties in interfacing my hardware accelerators with avalon bus so i abort this solution http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/unsure.gif .

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What specific problems do you have with designing Avalon MM hw accelerators? Avalon interfacing is very simple.

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originally posted by jeroen+dec 28 2006, 11:12 am--><div class='quotetop'>quote (jeroen @ dec 28 2006, 11:12 am)</div>

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<!--quotebegin-melomane@Dec 28 2006, 09:57 AM

for the "component version" i met some difficulties in interfacing my hardware accelerators with avalon bus so i abort this solution http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/unsure.gif .

--- Quote End ---

What specific problems do you have with designing Avalon MM hw accelerators? Avalon interfacing is very simple.

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=20256)</div>

[/b]

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Yes, First i&#39;m working with QuartusII 5.0 (SOPC builder)

And for my specifc problems : For example my hardware accelerator needs a data as entry much longer than 32 bits so can i do? especially when the data needs to be available at a specific clock cycle.

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originally posted by jeroen+dec 29 2006, 01:53 am--><div class='quotetop'>quote (jeroen @ dec 29 2006, 01:53 am)</div>

--- quote start ---

--- quote start ---

originally posted by melomane@dec 28 2006, 02:47 pm

--- quote start ---

originally posted by jeroen@dec 28 2006, 11:12 am

<!--quotebegin-melomane@Dec 28 2006, 09:57 AM

for the "component version" i met some difficulties in interfacing my hardware accelerators with avalon bus so i abort this solution http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/unsure.gif .

--- Quote End ---

What specific problems do you have with designing Avalon MM hw accelerators? Avalon interfacing is very simple.

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=20256)</div>

[/b]

--- Quote End ---

Yes, First i&#39;m working with QuartusII 5.0 (SOPC builder)

And for my specifc problems : For example my hardware accelerator needs a data as entry much longer than 32 bits so can i do? especially when the data needs to be available at a specific clock cycle.

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=20261)</div>

[/b]

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The only solution is to have multiple 32 bits registers and writes. The bus is only 32 bits wide. What kind of accelerator are you working on?

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=20267)</div>

[/b]

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My acelerators are: -Multiply Matrix (4,4)x(4,4) each element of the matrix take 8 bit so up to 32 bits entry http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif

-Scalar product(x1*x2+y1*y2+z1*z2)

-vectoriel Product which takes 2 Vectors V1(x1,y1,z1) V2(x2,y2,z2)

-Transformation from 2D to 3D coordinates