JPEG core with NiosII

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originally posted by jeroen+dec 29 2006, 01:53 am--><div class='quotetop'>quote (jeroen @ dec 29 2006, 01:53 am)</div>

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originally posted by melomane@dec 28 2006, 02:47 pm

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originally posted by jeroen@dec 28 2006, 11:12 am

<!--quotebegin-melomane@Dec 28 2006, 09:57 AM

for the "component version" i met some difficulties in interfacing my hardware accelerators with avalon bus so i abort this solution http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/unsure.gif .

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What specific problems do you have with designing Avalon MM hw accelerators? Avalon interfacing is very simple.

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Yes, First i&#39;m working with QuartusII 5.0 (SOPC builder)

And for my specifc problems : For example my hardware accelerator needs a data as entry much longer than 32 bits so can i do? especially when the data needs to be available at a specific clock cycle.

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The only solution is to have multiple 32 bits registers and writes. The bus is only 32 bits wide. What kind of accelerator are you working on?

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My acelerators are: -Multiply Matrix (4,4)x(4,4) each element of the matrix take 8 bit so up to 32 bits entry http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif

-Scalar product(x1*x2+y1*y2+z1*z2)

-vectoriel Product which takes 2 Vectors V1(x1,y1,z1) V2(x2,y2,z2)

-Transformation from 2D to 3D coordinates