JPEG core with NiosII

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originally posted by jeroen+dec 28 2006, 11:12 am--><div class='quotetop'>quote (jeroen @ dec 28 2006, 11:12 am)</div>

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<!--quotebegin-melomane@Dec 28 2006, 09:57 AM

for the "component version" i met some difficulties in interfacing my hardware accelerators with avalon bus so i abort this solution http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/unsure.gif .

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What specific problems do you have with designing Avalon MM hw accelerators? Avalon interfacing is very simple.

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Yes, First i&#39;m working with QuartusII 5.0 (SOPC builder)

And for my specifc problems : For example my hardware accelerator needs a data as entry much longer than 32 bits so can i do? especially when the data needs to be available at a specific clock cycle.