JPEG core with NiosII

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originally posted by jeroen+dec 27 2006, 11:45 pm--><div class='quotetop'>quote (jeroen @ dec 27 2006, 11:45 pm)</div>

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<!--quotebegin-melomane@Dec 26 2006, 08:37 AM

thanks for the information it&#39;s very important for me

but sorry i still have a question : how can i display the image in format jpeg after compressing it with my own jpeg compressor?

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Somehow transfer it to a PC. A flash card, a serial link.

I&#39;m currently working on a JPEG decoder, based on the reference implementation of the Indepedant JPEG Group. I&#39;m developing a few specific hardware accelerators; I have found that memory bandwidth is a major bottleneck (I also have a LCD controller that takes up quite some bandwidth http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif )

For example, my hardware Avalon MM IDCT core takes only 20 or so clock cycles to compute a full 8x8 IDCT including dequantization/descaling/rounding/clamping, but just transferring the coefficients and the resulting pixels components takes many more cycles (195 cycles just to load 64 coefficients in 32 writes (no looping), with a tightly coupled instruction and data memory). In the software version, these transfers took only a small percentage of the total computation time, but now it has become a major bottleneck. (I already have devised another way to speed this up).

Now I have sped up the IDCT, upsampling has become the major bottleneck, taking up over 60% of the total time, as this is basically just data copying.

My goal is to decode a 640x480 4:2:0 file in 100ms, though I think this isn&#39;t a realistic goal unless I use a full hardware JPG decoder http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/tongue.gif (it&#39;s around 550ms now)

I wonder if it&#39;s useful to use SDRAM, as currently I use the Async SRAM on a Nios development kit/Cyclone edition.

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Thank you Jeroen for your useful information and I think you have done a very good work even the speed up of the software version did not satisfied you. In previous work i have speed up an algorithm which treats the 3D images with a lot of multiplier

adder, and divide. These macroblocs, i have integrated it with two modes : first as custom instructions, and then as new component interfaced with NiosII processor

As a result i have speed up the software version taking over 70%(Version full custom instructions). For the "Component version" i met some difficulties in interfacing my Hardware accelerators with Avalon Bus so I abort this solution http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif . Please if you have some samples of Interfaces to Avalon (VHDL language in preference) in order to add my accelerators as new component. Send it to me and I will be very grateful to you http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

The device targeted is the stratixII (Simulated on Stratix professional Borad) and i have not tried to display some images before.