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Altera_Forum
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19 years agoJPEG core with NiosII
Hi Every body i am working on project : JPEG core on FPGA Probably i will use NiosII development kit with STRATIX board and i will iterface the JPEG core with the NiosII as a new component so i...
Altera_Forum
Honored Contributor
19 years ago --- Quote Start --- originally posted by tonnoplast@Jan 12 2007, 03:37 AM thank you badomen. i will have a look again to that documentations.
another question. do you think that is possible to catch datas from camera using pio port with irq? i mean, read that port everytime a signal(pxclk) shows a ready pixel byte, and then put that pixel on array.
thank you
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--- Quote End --- The interface doesn't look like it would support a PIO interface very well. I did a quick search and it looks like you are fed YUV using a clock source from the camera which comes back as back to back data. I recommend creating a component that takes the data from the camera, stuffs the data into a memory based FIFO, then having an interrupt fire when the FIFO reaches a certain length like half full for example. Then you can have a DMA pull the data out of your component. There could be better methods depending on your system architecture so I would explorer all possibilities before diving into the design. System Interconnect Fabric Custom Logic DMA <--- Your custom component (FIFO) <---- Camera