Interfacing Nios II with verilog module

Dear All,

I would like to start by saying I am quite new to HDL, FPGAs and the IDE. I've worked through a few digital design examples entirely but I feel like I want to tackle a larger problem using a the nios ii processor. Apologies for my noobiness in advance...

I have a small verilog module which I have written and compiles, however I would like to take the information from the module (two numbers in a 32-bit register each) and transfer it to a LCD/PC etc. After some thinking I think would be easiest to interface the verilog module with a nios ii processor as the verilog can be left to handle the high speed digital side, and the nios ii can be left to leisurely access and send/receive data with a PC. I've managed to work through a couple of very basic hello world nios ii designs, but none interface with a verilog module. However, I cannot seem to find any clear literature/guides on how I would go about starting with my verilog module and connecting it to my nios ii. Could anyone point me to any suitable resources, or offer some direct assistance?

Is it just a case of creating a couple of parallel I/O's and then instantiating them in my top-level entity (where my current verilog file sits)? Or do I need to create my own qsys component?

fwiw I'm using Quartus Prime Lite Edition with a Cyclone IV.

Thanks in advance.