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Altera_Forum
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7 years ago

Interfacing Nios II with verilog module

Dear All, I would like to start by saying I am quite new to HDL, FPGAs and the IDE. I've worked through a few digital design examples entirely but I feel like I want to tackle a larger problem ...
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Altera_Forum
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7 years ago

Hi,

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Is it just a case of creating a couple of parallel I/O's and then instantiating them in my top-level entity (where my current verilog file sits)? Or do I need to create my own qsys component?

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Yes, create a custom component and try to use.

All required information is in below like.

ftp://ftp.altera.com/up/pub/altera_material/14.0/tutorials/making_qsys_components.pdf

Let me know if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)