Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Interfacing Nios II with verilog module

Dear All, I would like to start by saying I am quite new to HDL, FPGAs and the IDE. I've worked through a few digital design examples entirely but I feel like I want to tackle a larger problem ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

XAUI, that is the perfect response, thanks so much for the easy clarification! Just to be 100% sure, when you say

"connect their exported conduit"

This is still enabling the "external_connection" Conduit in the System Contents map, correct? Just instead of assigning the conduit to a pin in pin planner, I will instantiate it to a sub module?

Many thanks again, it is really appreciated.

EDIT: To answer my own question, yes, still enable external_connection, many thanks again XAUI. :)