Honored Contributor
Honored ContributorHi, apologies for the long delay.
I've worked my way as far through the process as I can, though I as I'm still new there are many things I am not understanding. :oops: When I am generating my custom component, I get a wide variety of errors and warnings, and I'm not entirely sure as to what I need to change my ios to, in order to remove these. Can I have any suggestions or recommend any documentation which might help me decide? If you don't mind, I'd like to clarify what I'm intending to do here. I've created a verilog file which has some connections to external hardware (in this case, inbitstream, outbitstream, ledstatus and clk). The others I'd like to use with a NIOS II processor (incorrectbits, totalbits, start, and reset), as I will use the processor to send information to a PC for collection. My intention is to simply use the processor to 'start' the verilog module, by changing the state of 'start', then at some point later in time, it will change the state of 'start', and read the contents of incorrectbits and totalbits. Does this seem feasible in this scenario, or am I making some fundamental mistakes in my approach? I've attached a copy of my screen which may clarify, if not please ask and I will try my best to explain better. :) edit, I cannot attach a high enough res image to be of use, a sample can be found here: https://s15.postimg.cc/di9etn7rf/avaloninterface.png https://alteraforum.com/forum/attachment.php?attachmentid=15458&stc=1 Regards. https://alteraforum.com/forum/attachment.php?attachmentid=15457&stc=1
