Infamous Verify Failed

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originally posted by atjung+jan 19 2006, 05:03 pm--><div class='quotetop'>quote (atjung @ jan 19 2006, 05:03 pm)</div>

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<!--quotebegin-liangyi@Jan 19 2006, 12:36 AM

hi lemonoje,

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the memory in terms of timing works fine because i tested it using labview making calls to fs2&#39;s mdi to perform adderss/data bus tests, etc...

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But, how do you get the sdram pins work fine? The IDE display download info, then verify failed. Do you know that what will be done in verify process and what is the sdram pins state?

Thank you,

LiangYi

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If I understand what you are asking -- From talking with other users, if you have "boarderline" timing issues with memory doing peeks and pokes to a few memory locations will not always show a problem. Peeks and pokes only help show "major" timming issues or incorrectly connected memories.

If you hit the memory with a large block of data transfers the "boarderline" memory timing issues will start to up. For example

1) A DMA transfer to memory and back shows different results

2) If you load your program into SDRAM memory that has borderline timing issues, the processor is always accessing its next instruction so the memory problems will show up quickly by your program locking up.

3) If you use the IDE download a new program onto your board (writes are ok) and it fails verify (read fails) then one cause could be memory timing or I incorrectly connected the memory.

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this is exactly correct. peeks and pokes are good for identifying more major issues, although fs2&#39;s command line can load programs, etc... which will do large blocks of data transfer to test the timing exhaustively. i had been only doing peeks and pokes from the command line and everything seemed fine. verify was failing, as you put it, becuase of "boarderline" timing.

I would like to continue this discussion.

My system works fine, but sometimes I do a little change in the vhdl of a periphal and then the ide begins with Verify failed message...

Almost all changes don&#39;t cause problems, but a few changes do that and it seems there is no relationship with change in memory map or behavior.

Someone has a trick for that?

I found it!!

I was using a C0 output pll for the sdram_clk, and sometimes it dont achieve the desired phase shift for the sdram. Now I m using a E0 output pll, it is exclusive for external output pll and dont receive influence from internal routing.

I hope this can help another guys....

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originally posted by lemonoje@Feb 3 2006, 03:13 PM

great - glad you found the problem! that will probably also get rid of the jitter warning error that you get when it has to route internal

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Hi lemonoje i&#39;m getting started now with a stratix II (EP2S60F1020C4) and i had the same problem :

Verifying 03000020 ( 0%)

Verify failed

Leaving target processor paused.

I solved it by downloading an the board the standard.qpf file that i found i the directory:

altera\kits\StratixII_DSP_Kit-v1.1.0\Examples\HW\NiosII\example_designs\vhdl\standard

I have downloaded this file without compiling it.

I started Nios II IDE and runned a sample project unchecking Validate Nios II System ID before software downolad.

Everything works fine now.Good Luck and sorry if said uncorrect things but i&#39;m not so expert as you are! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/tongue.gif

Hi lemonje:

I have a question, what calculation did you do to find out the phase shift needed for SDRAM?? Where can I find out more about the calculation for the phase shift ?

I have been using the ALTERA example design all along throughout my project, and it has been fine until recently .

I just made a really huge JPEG decompresssion custom hardware component, I fitted it into the standard design example from Altera and somehow the verification started failing ... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif

Any idea??

And also i run my jpeg componenet at a different frequency (35Mhz) than my board freq (50Mhz), do you know how can I find out about any clock setup time or hold time I need to configure to read the memmory I built within the jpeg component?

Thanks in advance

Tony

Tony,

Check out the "SDRAM Controller with Avalon Interface" data sheet at :

datasheet (http://www.altera.com/literature/hb/nios2/n2cpu_nii51005.pdf) . At the very bottom you will find calculations for this.

With regards to the new component that runs at a different clock frequency than the CPU - have you hardended the signals across clock domains? If I&#39;m understanding, it sounds like you have a 50MHz clock for CPU and a 35MHz clock for the JPEG logic, which would require special care for the signals to cross each other to avoid instability.

I&#39;m very busy now, so sorry if the response time is a while...

Hi Lemonoje,

Thank you very much for your reply.

Yes, I found the doc from the Altera website, but I have been having difficulty finding the right tso and th from the compilation report. (i found max and min tco)

I was abit confused about the tsu and th becoz the th and tsu i got from the compilation report are quite different to the ones used in the example calculation in the doc.

For example, for th I had -0.963 for th but it&#39;s -5.6 ns in the example. Is this what I should be getting??

I tried -3.5ns shift for my sdram clock, and it seems to work fine. but the phase shift I should be using is actually -1.0ns according to my calculation (I haven&#39;t really tried this shift)

Yes, I was running my jpeg unit and NIOS II CPU at a different frequencies (35Mhz&50Mhz) but I decided to get the functionalities right first by running them both at 35 Mhz. It&#39;s easier to adjust the timing for SDRAM clock with lower frequency but i am not exactly sure how should I adjust it, more negative or more positive?.

I guess we have to do it through trial and error?

(MY SDRAM is the same as the one used in the example).

I compiled the standard Altera example,( I didn&#39;t modify it), and the tsu, th, max tco and min tco i found in the compilation report are :

1.405, -0.963, 4.127 and 2.362. ns

from the calculation using the same SDRAM, I got 2.161/2 ~= 1.0805ns. does this sound right?

Oh and also, do you happen to know that is it necessary to adjust the timing setting such as "issue one refresh command every ___ns", duration of refresh command ...etc if we lower the clock to 35 Mhz ?

Thank you very much.

Tony

I tried all the combinations of things to try and fix this problem.

I finally managed to get rid of the verify fail by including the sysid block. Other than that no changes were made. Strange.

I am trying to load the uClinux image for the DE2 board. I&#39;ve loaded the sof and pof and downloaded using the wiki instructions. I keep getting the following message..

Downloading 630KB in 7.7s

Verfying 00500000 <0%>

Verify failed between address 0x500000 and 0x502A19

Anybody know why I can&#39;t get this working? I&#39;m using the DE2_NET project and zimage_de2_net files. It should work but for me it doesn&#39;t. Please help me make this DE2 board more than a 500$ paper weight that blinks.