Infamous Verify Failed

Hi Lemonoje,

Thank you very much for your reply.

Yes, I found the doc from the Altera website, but I have been having difficulty finding the right tso and th from the compilation report. (i found max and min tco)

I was abit confused about the tsu and th becoz the th and tsu i got from the compilation report are quite different to the ones used in the example calculation in the doc.

For example, for th I had -0.963 for th but it's -5.6 ns in the example. Is this what I should be getting??

I tried -3.5ns shift for my sdram clock, and it seems to work fine. but the phase shift I should be using is actually -1.0ns according to my calculation (I haven't really tried this shift)

Yes, I was running my jpeg unit and NIOS II CPU at a different frequencies (35Mhz&50Mhz) but I decided to get the functionalities right first by running them both at 35 Mhz. It's easier to adjust the timing for SDRAM clock with lower frequency but i am not exactly sure how should I adjust it, more negative or more positive?.

I guess we have to do it through trial and error?

(MY SDRAM is the same as the one used in the example).

I compiled the standard Altera example,( I didn't modify it), and the tsu, th, max tco and min tco i found in the compilation report are :

1.405, -0.963, 4.127 and 2.362. ns

from the calculation using the same SDRAM, I got 2.161/2 ~= 1.0805ns. does this sound right?

Oh and also, do you happen to know that is it necessary to adjust the timing setting such as "issue one refresh command every ___ns", duration of refresh command ...etc if we lower the clock to 35 Mhz ?

Thank you very much.

Tony