Infamous Verify Failed

Tony,

Check out the "SDRAM Controller with Avalon Interface" data sheet at :

datasheet (http://www.altera.com/literature/hb/nios2/n2cpu_nii51005.pdf) . At the very bottom you will find calculations for this.

With regards to the new component that runs at a different clock frequency than the CPU - have you hardended the signals across clock domains? If I'm understanding, it sounds like you have a 50MHz clock for CPU and a 35MHz clock for the JPEG logic, which would require special care for the signals to cross each other to avoid instability.

I'm very busy now, so sorry if the response time is a while...