Hi lemonje:
I have a question, what calculation did you do to find out the phase shift needed for SDRAM?? Where can I find out more about the calculation for the phase shift ?
I have been using the ALTERA example design all along throughout my project, and it has been fine until recently .
I just made a really huge JPEG decompresssion custom hardware component, I fitted it into the standard design example from Altera and somehow the verification started failing ...
http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif
Any idea??
And also i run my jpeg componenet at a different frequency (35Mhz) than my board freq (50Mhz), do you know how can I find out about any clock setup time or hold time I need to configure to read the memmory I built within the jpeg component?
Thanks in advance
Tony