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Altera_Forum's avatar
Altera_Forum
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21 years ago

IDE FLash Programmer

I am having troubles with the Flash Programmer whne flashing the EPCS. The main problem is it isn't working. I have three different boards that all fail in the same way. Here is the console output from the flash programmer for one of the boards:

make: Entering directory `/cygdrive/d/workspace/doleksy/MC/mc/FPGA/Edit_Control_Right_2/software/right_edit/Debug'

Jul 27, 2004 4:37:12 PM - (INFO) nios2-flash-programmer: Launching Quartus Programmer to download:

d:/workspace/doleksy/MC/mc/FPGA/Common/target_board/right_t/system/right_t.sof

Pre-Reading 105KBytes of data from U21:

|----.----+----.----|

********************* (3.936 sec).

Erasing 2 Sectors:

|----.----+----.----|

********************* (2.513 sec).

Writing 128KBytes :

|----.----+----.----|

********************* (3.505 sec).

Verifying 128KBytes of data:

|----.----+----.----|

***********Jul 27, 2004 4:37:41 PM - (SEVERE) nios2-flash-programmer: Verification failure after write.

make: *** [epcs_controller_boot_rom_programflash] Error 8

make: Leaving directory `/cygdrive/d/workspace/doleksy/MC/mc/FPGA/Edit_Control_Right_2/software/right_edit/Debug'

All three boards fail verification at the same place. Can anyone tell me what if being verified from the above output? Is it verifying the FPGA configuration (.sof) or is it verifying my code? Any other ideas as to why the verification might fail. Thanks.

By the way, I have a call into my FAE but he hasn't returned it yet. I'll reply back with any info I get from him

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    Some additional info about my last post:

    Initially I was using an FS2 ISA-Nios to do all flash programming through the IDE. I suspected that maybe this didn't work correctly, so I started using the USB Blaster. No luck. Same error as stated above.
  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    After four hours with our distributor's FAE, we found the problem. It seems there is a bug in SOPC builder and/or quartus. In our case, we have boards with an EPCS but no flash. It seems that if the Nios 2 on the target board has no outputs (as would be the case with no flash), the compiler optimizes away something. Anyway, the kludge is to add a PIO and send it to a virtual pin. This prevents the optimization from happening.

  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    A Nios2 with no outputs...? So, just what is it supposed to do? Does it have an EPCS peripheral? Sorry if I'm missing something obvious...

    It just sounds like you have a Nios whose only purpose is to reprogram the EPCS; not a typical application. Quartus is supposed to eliminate logic blocks that have no outputs; theoretically, they have no effect on the system. Maybe it doesn't detect the hidden outputs in the EPCS peripheral?
  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    <div class='quotetop'>QUOTE </div>

    --- Quote Start ---

    It just sounds like you have a Nios whose only purpose is to reprogram the EPCS; not a typical application[/b]

    --- Quote End ---

    This is exactly what we are doing. With the Nios 2 you can program flash and EPCS devices from the IDE. It does this by configuring the FPGA with a minimal design used just for flashing. Since the EPCS has dedicated pins they don&#39;t come out of the Nios so some optimization was occuring that prevented the flashing of EPCS devices.

    More info on the new flashing came be found here:

    nios ii flash programmer&#39;s user guide (http://altera.com/literature/ug/ug_nios2_flash_programmer.pdf)