How to connect a VHDL file to existing NIOS up

If you just need a few control lines to your VHDL logic, just add some PIO peripherals and hook those up.

If you need an actual bus interface, look in the SOPC Builder manual for the part on adding custom components to an SOPC system.

Hi Mike,

if i use p/io and hook them up so that i can use them in the vhdl modules.

but is it possible to interrrupt the processor using same pios or

how to interrrupt the processor from a vhdl module.

regards

prasad

prasad,

It sounds like PIOs are not appropriate for what you'd like to do.

I'd recommend using Component Editor to create your component. Take a look at the SOPC Builder Chapter in the Quartus II Handbook, first.

For further information on how to do your address decoding, interrupt signaling, etc., just take a look at one of the many examples of this included with the kit. (interval timer, uart, jtag_uart, etc.)

Best Regards,

- slacker

--- Quote Start ---

originally posted by prasad_forums@Oct 27 2005, 05:25 AM

but is it possible to interrrupt the processor using same pios or how to interrrupt the processor from a vhdl module.

--- Quote End ---

When you create a PIO module with inputs, you can set it to generate an interrupt on level or edge detect on those inputs. The settings are in the PIO peripheral properties dialog, second tab.

I've created a few custom components through the editor in the SOPC Builder to import the VHDL designs.

If your VHDL file is to be used as slave, then it's pretty straightforward that you would need a clock, chip select, address, data in/out, read/write, and interrupt signals that tie to the Avalon Switch Fabric. Any signals that you want to connect to the outside world, leave those as exports when defining them. You can create the component with either register or memory cells, and make sure you specify if latency is needed in the read/write interface.

If your VHDL file is to be used as a master also, then you will need to add another clock (defined as master) and waitrequest signals. You can add another set of read/write and data in/out signals, but make sure you define them as masters. Thus, as a master, the data in will be defined as "readdata" and data out will be "writedata" from the Nios II perspective.

Here's a good place to look: http://www.altera.com/literature/manual/mnl_avalon_spec.pdf (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf)

This document will list off what signals you need to have when using component editor to create particular components. Usually for most interfaces you need these: address, data, chipselect, readdata, writedata, read, write, waitrequest (non-fixed latency), clk, reset (this set of signals is not appropriate for a tri-state components or is not enough for advanced components)