How to connect a VHDL file to existing NIOS up

Here's a good place to look: http://www.altera.com/literature/manual/mnl_avalon_spec.pdf (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf)

This document will list off what signals you need to have when using component editor to create particular components. Usually for most interfaces you need these: address, data, chipselect, readdata, writedata, read, write, waitrequest (non-fixed latency), clk, reset (this set of signals is not appropriate for a tri-state components or is not enough for advanced components)