How to connect a VHDL file to existing NIOS up

I've created a few custom components through the editor in the SOPC Builder to import the VHDL designs.

If your VHDL file is to be used as slave, then it's pretty straightforward that you would need a clock, chip select, address, data in/out, read/write, and interrupt signals that tie to the Avalon Switch Fabric. Any signals that you want to connect to the outside world, leave those as exports when defining them. You can create the component with either register or memory cells, and make sure you specify if latency is needed in the read/write interface.

If your VHDL file is to be used as a master also, then you will need to add another clock (defined as master) and waitrequest signals. You can add another set of read/write and data in/out signals, but make sure you define them as masters. Thus, as a master, the data in will be defined as "readdata" and data out will be "writedata" from the Nios II perspective.