Getting Nios to talk to on chip logic

You need to access the logic via the avalon bus.

I think you can use a generic 'pio' interface, but writing a avalon slave isn't that hard and will give greater flexibility (and probably remove some clock delays).

Do make sure you generate a 32bit slave - even if you ignore the high bytes.

Also the nios always asserts all 4 byte enables on reads.

Cobra,

I struggled with the nomenclature ... Megafunctions vs Components. I am in the same situation as you and need to create a Avalon new Avalon component.

In the QSYS , you can click on new under the library of components and that will allow you to generate a new component. There are some pre-defined interfaces.

Also check out this http://www.altera.com/literature/hb/qts/qsys_components.pdf

In I am still not sure how to add actual RTL to the component but believe in the case of an Avalon MM slave, possibly the same signals are used as the interface signals.

Once you have created a new component ... it will show up as a component in your library section.

Add the component to your desigh in QSYS and connect up all the signals ... it checks for this then

Run generate in QSYS and the new RTL design will be in the Quartus system where you can synthesize it.

I need to add a monitor to perform some monitoring of data coming out of an Avalon MM slave to perform ordering rules checks at speed.

Does anyone know if there is an Avalon MM monitor template since when I try to connect a slave to a slave it doesn't compute .

Thanks , Bob.

Cobra,

Went through the steps and new component generated this template. ... need to get the address width correct but I believe if it was a full slave , there would be a read section as well. I am interested in monitoring the output of a PCIe BAR0 master and only interested in the writes... so I have inputs only.

Assuming the connecting to QSYS is good, inside the component I will have a set of bus tracking state machines that can check ordering rules.

The PCIe BAR0 master targets memory, so one issue is how do I have a slave that is only a monitor which wants to look as the same address space as the memory.

I assume the address mapping for slaves in QSYS is used by QSYS to check for memory map issues and for known components like memory, probably drives internal

address decoders.

The other thing is that for a bus monitor an error or status register needs to feed back from state machines otherwise, synthesis should optimize out the cone of logic that does nothing !

`timescale 1 ps / 1 ps

module bus_tracker# (

parameter AUTO_CLOCK_SINK_CLOCK_RATE = "-1"

) (

input wire avs_address, // avalon_slave.address

input wire avs_begintransfer, // .begintransfer

input wire avs_beginbursttransfer, // .beginbursttransfer

input wire avs_burstcount, // .burstcount

input wire [7:0] avs_byteenable, // .byteenable

input wire avs_chipselect, // .chipselect

input wire avs_write, // .write

input wire [63:0] avs_write_data, // .writedata

input wire avs_output_enable, // .outputenable

input wire avs_lock, // .lock

input wire reset, // reset_sink.reset

input wire clk // clock_sink.clk

);

// TODO: Auto-generated HDL template

endmodule

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Total newbie question but what is the best way to get Nios to talk to custom on chip logic ? I'm setting up a special counter in logic that I'd like to have Nios control and read. Do I need to set up a custom connection in Qsys and use the Avalon interface or is there a more direct method ?

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Thanks Bob & DSL for the great advice. As a newcomer I'm finding the capabilities of these FPGAs incredible but sifting through the documentation and getting up to speed is kinda like drinking from a fire hose. I'll try your suggestions over the next few days. (Altera: a good tutorial here would go a long way)

OK, I think I may have found the most straight forward way (based on an example project that came with my dev kit):

1. Using Qsys, add a PIO component to the Nios processor (@dsl, I think this is what you mentioned in the beginning of your post). In my example, the two ports were named col and row.

2. Use the following avalon API calls to initialize the ports (Note COL_BASE and ROW_BASE will be define in system.h if the Qsys generation goes well).

# define col_in() IOWR_ALTERA_AVALON_PIO_DIRECTION(COL_BASE,0x0)

# define row_out() IOWR_ALTERA_AVALON_PIO_DIRECTION(ROW_BASE,0xf)

3. Use the following API calls to read and write to the ports:

# define col_read() IORD_ALTERA_AVALON_PIO_DATA(COL_BASE)

# define row_write(data) IOWR_ALTERA_AVALON_PIO_DATA(ROW_BASE,data)

I'm going to look into the Avalon Slave approach as well.

Cobra,

I was able to get an Avalon MM slave on the weekend and instantiated and compiling without error.

I have some work to do on the Avalon protocol... here is the neat part, templates are available that start you in the right direction... then add signals ... the signals names have to match predefinced names I believe inorder for the QSYS generate to correctly associate them and there is a button to generate an empty component RTL file . The file is not entirely empty as outputs are assigned to be quiescent.

So... I figure with the component RTL, just add finction to it.

I need a full slave to set component state machine parameters and a monitor side to the component that monitors the master output of interest.

I agree that examples are handy ... to make a start.

I was looking at the DMA component for the RTL function of the DMA but could not find it possibly it is encrypted.

Regards, Bob.