Honored Contributor
Honored ContributorCobra,
Went through the steps and new component generated this template. ... need to get the address width correct but I believe if it was a full slave , there would be a read section as well. I am interested in monitoring the output of a PCIe BAR0 master and only interested in the writes... so I have inputs only. Assuming the connecting to QSYS is good, inside the component I will have a set of bus tracking state machines that can check ordering rules. The PCIe BAR0 master targets memory, so one issue is how do I have a slave that is only a monitor which wants to look as the same address space as the memory. I assume the address mapping for slaves in QSYS is used by QSYS to check for memory map issues and for known components like memory, probably drives internal address decoders. The other thing is that for a bus monitor an error or status register needs to feed back from state machines otherwise, synthesis should optimize out the cone of logic that does nothing ! `timescale 1 ps / 1 ps module bus_tracker# ( parameter AUTO_CLOCK_SINK_CLOCK_RATE = "-1" ) ( input wire avs_address, // avalon_slave.address input wire avs_begintransfer, // .begintransfer input wire avs_beginbursttransfer, // .beginbursttransfer input wire avs_burstcount, // .burstcount input wire [7:0] avs_byteenable, // .byteenable input wire avs_chipselect, // .chipselect input wire avs_write, // .write input wire [63:0] avs_write_data, // .writedata input wire avs_output_enable, // .outputenable input wire avs_lock, // .lock input wire reset, // reset_sink.reset input wire clk // clock_sink.clk ); // TODO: Auto-generated HDL template endmodule
