FIFOed Avalon Uart

I do have a new version coming out but it is not tested enough yet. So I am not quite ready to give it out yet. Hopefully soon. I do have the new features you requested. I guess I could release it as a kind of beta so you could try it out if you like.

Longshot

Be aware of when using a PC serial port, its Tx FIFO will continue to empty itself after changing CTS. To ensure no more data is sent from the PC, go into "Port Settings - Advanced" on the Control Panel and set the Tx FIFO to 1.

I don't use this UART but is it able to set CTS when the FIFO is full, or when it's nearly full?

--- Quote Start ---

originally posted by billooj@Sep 27 2006, 11:24 AM

i'm using the fifoed avalon uart with hw cts rts control flow to send data to a bluetooth tranceiver at 921kbps.

the bluetooth tranceiver send the data to a pc through a virtual com port configured at 921 kbps too.

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=18469)

--- quote end ---

--- Quote End ---

Do you have a bluetooth transceiver that its directly connected to the fpga ?

I am still searching for a bluetooth solution to connect my fpga via a uart for a wireless terminal port.

It would be cool if this is a 3,3V module that can directly be connected to a fpga and transmits the uart data to a pc f.e. and there i could open a "com" port from a application software.

Any link to such a device is greatly welcome as i will include bluetooth as soon as possible

Regards.

jason : Go to fifoed avalon uart project (http://www.niosforum.com/pages/project_details.php?p_id=89&t_id=18), signals behavior according to FIFO state are described in project files.

Thx for your suggestion, I&#39;ll see.

For the moment : When UART is directly connected to PC with RS232 cable, there is no flow control at 921K for data from FPGA to PC, so there is no double data byte sent.

When UART is connected to PC through Bluetooth module and virtual COM port, there is flow controls at 921K for data from FPGA to BT module, and there is double data bytes sent.

mschmitt : There are many complete Bluetooth module including antenna (BlueGiga, Stollman, Free2move, National Semiconductors, Philips NXP) that can be directly connect with an FPGA for Reset, RX, TX, RTS, CTS in 3,3V.

I looked for a module 2.0 + EDR that can go at 3Mbit/s, but it seems that the Serial Port Profile protocole can&#39;t go over 921K, like 1.2 and 1.1 BT modules.

Thanks Billooj !

I just had visited National&#39;s web site and found the lmx9830. As we design microwave stuff this is very easy to be integrated into our target pcb&#39;s

The only thing left seems to be FifodUart and somebody shouting it works @ 931kbit/sec ... :-))

But i am still seeking for other chips for this purpose.

Longshot :

If you think you have the RTS feature i requested ready i could give it a try @ 115200 bit/sec. Hope you have also fixed the wrong clock speed. The orignal zip showed a wrong input clock. assuming the clock that feeds the sopc pll is the clock speed and not c0...c2 as connected via sopc.

Thanks to all here.

Regards.

Michael

Another bug found, the parity bit is inverted.

IzI

correction:

there was no parity problem, i was programming the wrong file.

uCLinux:

I tested the Fifoed uart under uCLinux and if seems to work OK. With the original Altera Uart we had a lot of UART buffer overruns, just by pressing the up arrow in the console, there was no way of pasting text into the console:

ttyS0: 1 input overrun(s)

We currently use FIFOs of length 512 which still consumes the same amount of M4K blocks (4) as FIFOs of length 16.

IzI

Have you solved my problem?

I have a Nios project that talks to a PC. Apparently the Nios sends a buffer of data so fast that it overruns the PC without any flow control. Messages from PC to Nios don&#39;t seem to be a problem.

Hardware flow control (PC tells Nios to go or wait) would probably be the solution, but as I understand the standard Nios UART (included with Quartus/Nios 6) the CTS/RTS are simply status bits that software can read, don&#39;t really do anything.

My understanding is that the upgraded Uart you have provided allows Nios to use hardware flags to allow/stop incoming communication. Would it also serve in my case? That is, will it stop/resume transmission from Nios to PC in response to hardware handshakes from PC?

And could you please confirm the polarity of the handshake signals?

Thanks in advance...you may have been a lifesaver to me

Michael

Trying to use this Fifoed Uart for low data rates, but not understanding the docs. A simple word description of what controls the CTS, RTS is needed. The perl is too obtuse for me.

I have selected &#39;use cts rts&#39;, and a fifo size of 16. What do I gain or not gain by selecting &#39;hw cts&#39;?

When I use the standard &#39;FAST&#39; compile option, I assume the packaged component/driver will properly handle the flow control:

1) The uart will not send data to the DCE (a modem in my case) unless# CTS is asserted and there is something in the uart tx fifo to send.

2)# RTS will be asserted only when the uart rx fifo is full.

3) My app only needs to r/w to the circular sw buffer and does not need to inspect/control CTS,RTS registers or handle the data xfer between circular sw buffer and uart.

Am I wrong in my assumptions?

On the configuration tab, the checkbox "Include CTS/RTS pins & control register bits" will only create register bits to control/read these signals. There&#39;s no hardware connection between the read/write FIFO&#39;s and CTS/RTS pins. It&#39;s up to SW.

On the MISC tab, the checkbox "Create hardware CTS input" looks like it will throttle the NIOS & prevent it from sending when the connected device asserts CTS.

However, there&#39;s no provision in hardware for NIOS to tell the connected device that its receive buffer is full with RTS (which is what I want!).

Longshot--any chance of getting RTS support in there?

Thanks

I figured out how to add RTS flow control in hardware using the UART with FIFO&#39;s.

Add the FIFO&#39;ed UART component in SOPC builder. Check the configuration box to add RTS & CTS register bits. Generate the system.

When it&#39;s done generating, open uart.vhd and edit:

Look for:

rts_n <= NOT rts_control_bit;

Comment out this line and add the following:

  -- Generate RTS
  rts_c: process (clk, reset_n)
  begin  -- process rts_c
    if reset_n = '0' then               -- asynchronous reset (active low)
      rts_n <= &#39;1&#39;; -- 1=OK to send
    elsif clk&#39;event and clk = &#39;1&#39; then  -- rising clock edge
      if (rx_used(rx_used&#39;left) = &#39;0&#39;) then -- FIFO is < 1/2 full
        rts_n <= &#39;0&#39;;  -- inverted at tranceiver
      else
        rts_n <= &#39;1&#39;;
      end if;
    end if;
  end process rts_c;

This asserts RTS when the receive FIFO is 1/2 full.

Note that reading the RTS bit in the UART register will not reflect the state of the pin. You&#39;d have to find where rts_control_bit is read and substitute rts_n.

Note that RTS is inverted at the RS232 tranceiver, so the levels you&#39;ll see on the port are reversed from the code.

Hope this helps. I tested it & it works well on my system.