FIFOed Avalon Uart

On the configuration tab, the checkbox "Include CTS/RTS pins & control register bits" will only create register bits to control/read these signals. There's no hardware connection between the read/write FIFO's and CTS/RTS pins. It's up to SW.

On the MISC tab, the checkbox "Create hardware CTS input" looks like it will throttle the NIOS & prevent it from sending when the connected device asserts CTS.

However, there's no provision in hardware for NIOS to tell the connected device that its receive buffer is full with RTS (which is what I want!).

Longshot--any chance of getting RTS support in there?

Thanks