FIFOed Avalon Uart

Trying to use this Fifoed Uart for low data rates, but not understanding the docs. A simple word description of what controls the CTS, RTS is needed. The perl is too obtuse for me.

I have selected 'use cts rts', and a fifo size of 16. What do I gain or not gain by selecting 'hw cts'?

When I use the standard 'FAST' compile option, I assume the packaged component/driver will properly handle the flow control:

1) The uart will not send data to the DCE (a modem in my case) unless# CTS is asserted and there is something in the uart tx fifo to send.

2)# RTS will be asserted only when the uart rx fifo is full.

3) My app only needs to r/w to the circular sw buffer and does not need to inspect/control CTS,RTS registers or handle the data xfer between circular sw buffer and uart.

Am I wrong in my assumptions?