FIFOed Avalon Uart

jason : Go to fifoed avalon uart project (http://www.niosforum.com/pages/project_details.php?p_id=89&t_id=18), signals behavior according to FIFO state are described in project files.

Thx for your suggestion, I'll see.

For the moment : When UART is directly connected to PC with RS232 cable, there is no flow control at 921K for data from FPGA to PC, so there is no double data byte sent.

When UART is connected to PC through Bluetooth module and virtual COM port, there is flow controls at 921K for data from FPGA to BT module, and there is double data bytes sent.

mschmitt : There are many complete Bluetooth module including antenna (BlueGiga, Stollman, Free2move, National Semiconductors, Philips NXP) that can be directly connect with an FPGA for Reset, RX, TX, RTS, CTS in 3,3V.

I looked for a module 2.0 + EDR that can go at 3Mbit/s, but it seems that the Serial Port Profile protocole can't go over 921K, like 1.2 and 1.1 BT modules.