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Altera_Forum's avatar
Altera_Forum
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15 years ago

DMA problem

Hi,

I'm transfering data (video frames) from sdram to component i build (using sopc component editor) by DMA controller.

For each transaction the DMA transfers one frame line, data is then sent to LCD.

In the beginning of each frame i'm asserting IRQ to nios (from a component i build just for the purpose of asserting IRQs).

The control over the DMA from software seems to be weak.

I can't control the timing of DMA transactions.

When i'm using HAL commands, the DMA response is much slower then when using IOWR commands, but transfering the correct data.

the problem is, that this way, DMA response is much too late.

When I'm using IOWR, the DMA response is very good, but transfering the wrong data, seems like DMA transfers data from wrong address.

my questions:

1) How can I de-activate the interrupt signal in software? (the component that is asserting the IRQ is "user defined")

Is there a way of controlling specific signals in my component by IOWR commands?

2) How can i access the "readyfordata" signal from software (I mean from the nios side)? What way do i have to control the DMA beside "readyfordata" signal?

Any help is appreciated :)

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Did you properly handle the data cache? After your software writes the video data to the sdram, the data cache must be flushed before the DMA starts reading it. This could explain why you don't see the correct data on the output.

    Which DMA controller are you using? I know that at least the SGDMA has an interrupt mask register that can be used to disable IRQs.

    To control signals in your component, you need to add an Avalon Slave interface to it and connect it to the CPU data master. You'll then be able to use IOWR/IORD to access your component.

    "readyfordata" is a hardware signal and can't be controlled by software. To control the DMA, use either the Hal functions or IOWR to the control register.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Of course you could modify your own component so that it stalls the DMA until the new frame arrives. It is probably the easiest solution to have a correct timing.

    It is quite easy to do with the SGDMA, I guess it must be possible with the other DMAs too.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thank you very much for your response, i was off the forum for a while...

    I solved the DMA problem using "readyfordata" signal and correct timing.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi;

    I want to get the status of the eop signal form de CVI, and I don't know how to access to this signal, do you have any idea about that ?

    thank you!
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi,

    I don't know what is CVI.

    If you want to get the eop status you can read the DMA status register.

    you can use IORD_ALTERA_AVALON_DMA_STATUS(base).

    don't forget to include "altera_avalon_dma_regs.h"

    hope this helps
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi thank you for your answer, but this is not what I'm looking for. the CVI is the video clocked in, so I need to know the end of each frame.

    thank you !

    Rabia