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Altera_Forum
Honored Contributor
Honored ContributorDMA problem
Hi, I'm transfering data (video frames) from sdram to component i build (using sopc component editor) by DMA controller. For each transaction the DMA transfers one frame line, data is then se...
Altera_ForumHonored Contributor
Honored ContributorDid you properly handle the data cache? After your software writes the video data to the sdram, the data cache must be flushed before the DMA starts reading it. This could explain why you don't see the correct data on the output.
Which DMA controller are you using? I know that at least the SGDMA has an interrupt mask register that can be used to disable IRQs. To control signals in your component, you need to add an Avalon Slave interface to it and connect it to the CPU data master. You'll then be able to use IOWR/IORD to access your component. "readyfordata" is a hardware signal and can't be controlled by software. To control the DMA, use either the Hal functions or IOWR to the control register.
