ddr3 sdram controller (UniPHY) afi_half_clk doesn't work but status signals work fine

I have build a qsys system, that niosII connects a mm bridge then connects with ddr3 controller. I use afi_clk to drive the nios II. And then I export the afi_half_clk to external qsys to drive a counter, which msb connects a led.

Then I program the FPGA with the design. I can see ddr3 status signals good. Both init_done and cal_done assert. But the led is driven by afi_half_clk doesn't blink. Meanwhile, I run a hello_world program in the FPGA, it works. "Hello World" is printed in JTAG console. Nios is driven by afi_clk. So it looks like afi_clk is working. But when I try to write and read the ddr3 through program:

# include <stdio.h># include "..\hello_world_bsp\HAL\inc\io.h"# include "..\hello_world_bsp\system.h"

int main()

{

printf("Hello from Nios II!\n");

unsigned int readVal;

IOWR_32DIRECT(DDR3_72_BASE, 0x08, 1);

readVal = IORD_32DIRECT(DDR3_72_BASE, 0x08);

printf("The value read back is %u", readVal);

return 0;

}

It gives me the error "Downloading ELF Process failed". This error doesn't bring any information but it seems indicate the hardware error. So how it can be that the status signals are fine and afi_clk is working, but afi_half_clk is not toggling?

I also attached my qsys system screenshot. If anyone has any idea, please give some hints. Thanks in advance.